ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) 2015
DOI: 10.1109/esscirc.2015.7313824
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A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links

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Cited by 8 publications
(8 citation statements)
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“…Figures 19 and 20 show the eye diagrams at the input of the equalizer for 400 Mb/s, 1.25 Gb/s, and 2.5 Gb/s for 10-and 50-m length SI-POF. Nevertheless, we propose to use the following simple figure of merit [11] FOM ¼ BitRate Gb=s ð Þ⋅Fiberlength m ð Þ Power mW ð Þ (18) Table I summarizes the main performances of the proposed equalizer and compares them with the results of other adaptive equalizers aimed for the same channel (SI-POF). Figures 21 and 22 show the eye diagrams at the output of the equalizer for 400 Mb/s, 1.25 Gb/s, and 2.5 Gb/s for 50-and 10-m length SI-POF, respectively, with the three loops operating normally.…”
Section: Measurement Resultsmentioning
confidence: 99%
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“…Figures 19 and 20 show the eye diagrams at the input of the equalizer for 400 Mb/s, 1.25 Gb/s, and 2.5 Gb/s for 10-and 50-m length SI-POF. Nevertheless, we propose to use the following simple figure of merit [11] FOM ¼ BitRate Gb=s ð Þ⋅Fiberlength m ð Þ Power mW ð Þ (18) Table I summarizes the main performances of the proposed equalizer and compares them with the results of other adaptive equalizers aimed for the same channel (SI-POF). Figures 21 and 22 show the eye diagrams at the output of the equalizer for 400 Mb/s, 1.25 Gb/s, and 2.5 Gb/s for 50-and 10-m length SI-POF, respectively, with the three loops operating normally.…”
Section: Measurement Resultsmentioning
confidence: 99%
“…A direct comparison with other adaptive equalizers is not easy, as they either use different technology or provide measures only for single bit rate. Nevertheless, we propose to use the following simple figure of merit [11] FOM…”
Section: Measurement Resultsmentioning
confidence: 99%
See 2 more Smart Citations
“…The inputs of the XOR are the data signal and the output of the FF, whereas the output of the XOR gate goes to the FF, which is controlled by the clock signal. This structure presents a major drawback, which is the necessity of a very careful adjustment of the delay time of the cells to ensure a correct operation [2]. The second one is formed by an AND gate, which processes both the data and clock signals and whose output goes to a frequency divider.…”
mentioning
confidence: 99%