A 2.2GHz sub-sampling PLL with 0.16ps&lt;inf&gt;rms&lt;/inf&gt; jitter and &amp;#x2212;125dBc/Hz in-band phase noise at 700&amp;#x00B5;W loop-components power

Gao, Xiang; Klumperink, Eric A.M.; Socci, Gerard; Bohsali, M.; Nauta, Bram

doi:10.1109/vlsic.2010.5560323

Cited by 21 publications

(20 citation statements)

References 4 publications

(8 reference statements)

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“…When the ADPLL locks, each rising edge of CK REF aligns that of CK OUT for every 12 output periods. The divideby-12 divider, the BBPFD, and the retimed DFF are power downed to save the power [5].…”

confidence: 99%

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A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of $-$252.5 dB

Lee

Zeng

Liu

2013

IEEE Trans. Circuits Syst. II

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A subharmonically injection-locked all-digital phaselocked loop (ADPLL) is presented to achieve both low power and low phase noise simultaneously. This ADPLL uses a bang-bang phase detector to maintain the phase locking without a time-todigital converter, and the dividers can be disabled to reduce the power. In addition, a subharmonically injection-locked technique is used to achieve a low phase noise. This ADPLL is fabricated in a 40-nm complementary metal-oxide-semiconductor technology. Its power consumption is 3.661 mW for a supply voltage of 1.1 V. The measured phase noise is equal to −122.33 dBc/Hz at an offset frequency of 1 MHz. The integrated root-mean-square jitter is 123.4 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure of merit is equal to −252.5 dB.Index Terms-All-digital phase-locked loop (ADPLL), injection locked, subharmonically.

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confidence: 99%

“…Thus, a BBPD is needed. In addition, the dividers [5] and a DSM can be turned off to save the power by using this BBPD. Since the timing error between CK REF and CK OUT is small enough, the subharmonically injectionlocked technique [6], [7] can be adopted to lower the phase noise further.…”

Section: Introductionmentioning

confidence: 99%

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of $-$252.5 dB

Lee

Zeng

Liu

2013

IEEE Trans. Circuits Syst. II

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“…To achieve a low phase noise, the PLLs using the sub-harmonically injection-locked [6,9] and the sub-sampling [10][11] techniques have been realized. An ADPLL using the sub-harmonically injection-locked technique is presented in [6].…”

Section: Introductionmentioning

confidence: 99%

“…The FAC measures the outputs of these three DFFs to obtain the P TH and N TH to avoid the duty cycle and the harmonic locking issues. Initially, the signal INJ_EN is high and the FAC generates two digital codes, Code DLF of CK OUT is located at the center of the injection pulse INJ [10], which tolerates the PVT variations. Fig.…”

Section: Introductionmentioning

confidence: 99%

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider

Zeng

Kuan

Liu

2015

IEEE Trans. Circuits Syst. II

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A sub-harmonically injection-locked all-digital phase-locked loop (ADPLL) without a main divider is presented. It achieves not only low power, but also low phase noise over the process, voltage and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without time-to-digital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process, it consumes 3.04mW under a standard supply of 1.1V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4dBc/Hz at 1MHz offset. The integrated rms jitter is 109.6 fs for the offset frequency from 1kHz to 100MHz. The calculated figure-of-merit is equal to -254.39 dB.[7] is presented. It needs the multiple phase/frequency detectors and charge pumps. Moreover, the current mismatch of a charge pump may degrade the injection timing to induce a large reference spur.Some divider-less PLLs [6-7, 10-11] can turn off the main divider to save the power. However, the main divider is still required. In this paper, a sub-harmonically injection-locked ADPLL without a main divider is presented. To ensure the correct frequency, a frequency acquisition algorithm is presented. In addition, the injection timing is self-adjusted by using the proposed pulse generator. This paper is organized as follows. In Section II, the proposed ADPLL is presented. The experimental results are shown in Section III, and the conclusions are given in Section IV. II. CIRCUIT DESCRIPTION A. Frequency Acquisition AlgorithmAssume that an LC digitally-controlled oscillator (DCO) is implemented with the Metal-Oxide-Metal capacitors and the varactors controlled by the digital control codes, respectively. For this ADPLL, the frequencies of the reference clock, CK REF , and the output clock, CK OUT , of the DCO are f REF and f OUT , respectively. Let f REF =400MHz and the multiplication ratio N=12. A BBPD is used as a phase detector (with less frequency tracking ability), and the frequency tracking range is about 40MHz according to the behavior simulations. Therefore, to tolerate the PVT variations, the transfer curves of this LC DCO are divided into 32 bands and every band has a frequency range of 40MHz to overlap with each other. The tuning range of this DCO covers 4.3~5.4GHz. The frequency step is 1.25MHz/ code and the overlapped range between two consecutive bands is 25MHz. The frequency deviation, Δf, exists between CK REF and CK OUT and it is expressed as 1549-7747 (c)

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“…Chapter 5 elaborates design techniques that can boost the power efficiency of the SSPLL even further [35]. We aim to reduce the loop-components power of the SSPLL in Chapter 4 by an order of magnitude while keeping its superior in-band phase noise performance.…”

Section: Thesis Organizationmentioning

confidence: 99%

Low jitter low power phase locked loops using sub-sampling phase detection

Gao¹

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A 2.2GHz sub-sampling PLL with 0.16ps<inf>rms</inf> jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power

Cited by 21 publications

References 4 publications

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of $-$252.5 dB

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of $-$252.5 dB

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider

Low jitter low power phase locked loops using sub-sampling phase detection

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