A 160 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu{\rm A}$&lt;/tex&gt;&lt;/formula&gt; Biopotential Acquisition IC With Fully Integrated IA and Motion Artifact Suppression

Helleputte, Nick Van; Kim, Sun‐Young; Kim, Hye-Jung; Kim, Jong Pal; Hoof, Chris Van; Yazıcıoğlu, Refet Fırat

doi:10.1109/tbcas.2012.2224113

Cited by 135 publications

(12 citation statements)

References 20 publications

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“…For controlling the amplitude, the closed loop gains of the respective blocks should be designed properly. Accordingly, considering of the gain characteristics (40 dB) of the acoustic signal (<10 kHz) [1,2,3,4,5,6,7,8,9], the gain of the preamplifier is designed to be 25 dB; while the gain of the pseudo-PLL closed loop should be 15 dB.…”

Section: The Principle Of the Proposed Technique 1) The Structure Witmentioning

confidence: 99%

“…Recently, technology's impact on hearing aid system has begun to accelerate [1,2,3,4,5,6,7,8,9,10,11,12]. Since the hearing aid readout circuit's performance is determined by the ability of the bio weak signal detection, the key parameters such as distortion and dynamic range are necessary to be improved, especially with the ultra low supply voltage.…”

Section: Introductionmentioning

confidence: 99%

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An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique

Kou

Cheng

2018

IEICE Electron. Express

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We present an accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique. Compared with the conventional techniques, the technique replaces the typical oscillation approaches with a special pseudo-PLL feedback loop, which is able to partially amplify and directly convert the acoustic signal into the PWM signal without OTAs and comparators. Since the partially amplifying pseudo-PLL loop has the large open loop gain characteristic with the ultra low supply voltage, the accuracy of the large output signal should be maintained with the limited power dissipation. Fabricated with a 0.18 µm standard CMOS process, with the 1.2 V supply voltage and the input sine wave 1 KHz, the signal to noise and distortion rate (SNDR) achieves 55 dB@1 V p-p output voltage with the bandwidth 20 kHz. Moreover, the circuit's power consumption is 9 µW.

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Section: The Principle Of the Proposed Technique 1) The Structure Witmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique

Kou

Cheng

2018

IEICE Electron. Express

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“…A higher-order HPF is one of the effective solutions to attenuate these low frequency artifact signals. In addition, many bio-signal detection circuits were reported to overcome external offsets caused by polarization of the skin-electrode interface, and internal offsets caused by process variations [ 4 , 5 , 6 ]. For a comfortable connection between circuit and body, dry electrode rather than wet electrode is used in recent biopotential measuring device.…”

Section: Introductionmentioning

confidence: 99%

“…Insufficient input impedance is enhanced by a capacitive impedance boosting loop (CIBL). The previously reported active impedance boosting sub-circuit using positive feedback requires additional power consumption [ 4 ]. The CIBL in this design is implemented using a passive capacitor, and does not require additional power consumption.…”

Section: Introductionmentioning

confidence: 99%

Fully Integrated Biopotential Acquisition Analog Front-End IC

Song

Park

Kim

et al. 2015

Sensors

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A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

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“…Figure 1 shows the block diagram in a wireless neural recording microsystem [ 1 ], where an analog-to-digital converter (ADC) is used for digitizing neural data recorded at each electrode. These neural data include several components, like local field potentials (LFPs), extracellular spikes and motion artifacts [ 18 , 19 , 20 , 21 , 22 ]. To record these neural data without saturating from large artifacts, it requires a wide dynamic range for data acquisition.…”

Section: Introductionmentioning

confidence: 99%

A High Performance Delta-Sigma Modulator for Neurosensing

Zhao

et al. 2015

Sensors

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Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

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A 160 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm A}$</tex></formula> Biopotential Acquisition IC With Fully Integrated IA and Motion Artifact Suppression

Cited by 135 publications

References 20 publications

An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique

An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique

Fully Integrated Biopotential Acquisition Analog Front-End IC

A High Performance Delta-Sigma Modulator for Neurosensing

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