A 160 Gbit/s large-capacity ATM switching system using a dynamic link speed controlled switch architecture

Doi, Yukihiro; Yamada, Hiroyuki

doi:10.1109/glocom.1993.318092

Cited by 1 publication

(1 citation statement)

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“…The rapid increase in telecommunication traffic demands large throughput over 1 Tbit/s for ATM switching systems by 2010 [1]. The maximum switching capacity reported to date for LSI-based ATM switching systems is 160 Gbit/s [2]. One limitation for expanding this switching capacity into Tbit/s order is the memory access speed of the semiconductor memory devices used in cell-buffer storage [3,4].…”

Section: Introductionmentioning

confidence: 99%

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Tahara¹

1999

Supercond. Sci. Technol.

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We have developed a 10 GHz 32-bit delay-line memory, using a semiconductor crossbar switch and a YBa2Cu3O7- coplanar delay line. For use in the high-speed (10 GHz) cell-buffer storage of large-throughput (1 Tbit/s) asynchronous transfer mode (ATM) switching systems, this memory must be fairly reliable. To evaluate the reliability of the operation, therefore, we measured the clock-frequency and temperature margins and the temperature dependence of the bit-error rate. At 64 K, this memory has a capacity of 32 bits with a clock frequency of 9.89±0.11 GHz. In general, clock frequencies of communication systems are strictly managed so that the margins are less than 10-6. Therefore, the frequency margin of this memory (~2 × 10-2) is wide enough for use in communication systems. The temperature margin was 71.5±4.3 K at 10 GHz and 33 bits. This memory offered error-free operation (BER < 10-13) at 71.5±3.5 K. These temperature margins are wide enough to be controlled by a cryocooler. These results show that the memory offers reliability and that it can be applied to high-speed ATM cell-buffer storage.

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Section: Introductionmentioning

confidence: 99%

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Tahara¹

1999

Supercond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

A 160 Gbit/s large-capacity ATM switching system using a dynamic link speed controlled switch architecture

Cited by 1 publication

References 6 publications

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

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