A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Chun, Ki Chul; Kim, Yong Ki; Ryu, Yesin; Park, Jaewon; Oh, Changhoon; Byun, Young Yong; Kim, So Young; Shin, Dong Hak; Lee, Jun Gyu; Ho, Byung-Kyu; Park, Min Sang; Cho, Seong-Jin; Woo, Seung Han; Moon, Byoung Mo; Kil, Beomyong; Ahn, Sungoh; Lee, Jae Hoon; Kim, Soo Young; Choi, Seouk-Kyu; Jeong, Jaeeun; Ahn, Sung-Gi; Kim, Jihye; Kong, Jun Jin; Sohn, Kiwon; Kim, Nam Sung; Lee, Jung-Bae

doi:10.1109/jssc.2020.3027360

Cited by 24 publications

(3 citation statements)

References 10 publications

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“…3) ON-DIE ECC Fig. 14(a) shows a multi-bit error for the structure of DDR5 memory having four system ECCs and three OD-ECCs with a hamming code of (72,64) and (104,96), respectively [73,74]. By simultaneously applying the system ECCs and OD-ECCs, the uncorrectable bit error rate (UBER) can be decreased to one third.…”

Section: ) Advanced Crcmentioning

confidence: 99%

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Review of Memory RAS for Data Centers

Lee,

Kim,

Kim

et al. 2023

IEEE Access

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Multi-bit error and downtime due to uncorrectable error (UE) in a dual in line memory module (DIMM) have received great attention in data centers for its high repair or replacement cost. These problems can be alleviated by utilizing ECC (Error Correction Code) technology, which enables prompt error correction during initial occurrences and prediction of future UEs based on recurring error patterns. The technologies for addressing errors can be categorized into reliability, availability, and serviceability (RAS), and need to be optimized using various parameters such as accuracy, recall, F-measures, and cost reduction. This paper describes an overview of the current RAS technologies and trends in memory for data centers, which includes an analysis of conventional ECC technologies and their recent developments. Once UEs cannot be completely eliminated with ECCs, page offline methods based on analysis on error patterns and characterization of UE can be performed. Recent research trends for reducing memory capacity wasted by UE and page offline have been towards on-die ECC in high bandwidth memory architecture. INDEX TERMSCorrectable error (CE), error correction code (ECC), memory reliability, availability, serviceability (RAS), and uncorrectable error (UE).

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Section: ) Advanced Crcmentioning

confidence: 99%

“…High bandwidth memory 2 extension (HBM2E) [73] applied SECDED simultaneously to OD-ECC and the system ECC in Fig. 27.…”

Section: Future Workmentioning

confidence: 99%

Review of Memory RAS for Data Centers

Lee,

Kim,

Kim

et al. 2023

IEEE Access

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“…Therefore, DRAM researchers and producers studied the placement of ECCs on DRAM dies, which are called inmemory ECCs [16], [17], [18]. Despite many difficulties in applying in-memory ECCs to DRAM [17], results have been reported for DRAM chips with in-memory ECCs [19], [20], [21].…”

Section: Introductionmentioning

confidence: 99%

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

Han

Lee

et al. 2021

IEEE Access

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Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

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History of MOS Memory Evolution on DRAM and SRAM

Koyanagi

2023

75th Anniversary of the Transistor

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A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Cited by 24 publications

References 10 publications

Review of Memory RAS for Data Centers

Review of Memory RAS for Data Centers

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

History of MOS Memory Evolution on DRAM and SRAM

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