A 14b 20mW 640MHz CMOS CT /spl Delta//spl Sigma/ ADC with 20MHz Signal Bandwidth and 12b ENOB

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

“…Sigma-Delta (ΣΔ) architectures, either continuous-time (CT) [3] or switched-capacitor (SC) [4][5][6] can simultaneously achieve high BW, high resolution, and low power. Multi-bit SC implementations of ΣΔ modulators (ΣΔM) can reach FM 1 of the order of 0.5 pJ to 0.7 pJ [4][5][6] and FM 2 =0.54 pJ .…”

“…mm 2 is obtained in [4]; however, the decimation filter is not taken into account. In [3] a CT-ΣΔ realization includes the decimation filter which dissipates an additional power of 50% and occupies an area of 30% of the ΣΔM. A high energy efficiency with FM 1 =0.3 pJ is measured, but when area is also taken into account we end up with FM 2 =2 pJmm 2 .…”

A clock jitter error compensation and auto-tuning structure for continuous-time $$\Upsigma\Updelta$$ modulators

“…During recent years, continuous-time sigma-delta (CTRD) modulator has become a feasible and suitable ADC approach for wireless and wired communications due to low power consumption, wide bandwidth and small area with respect to its discrete-time (DT) counterpart [1,2]. However, CTRD modulators suffer a lot from clock jitter because of their higher sensitivity than DTRD ones.…”

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

“…However, the multi-bit M is prone to the Digital to Analog Converter (DAC) nonlinearity due to lithographic errors during fabrication that ultimately limit the Signal-toNoise-and-Distortion Ratio (SNDR) to around 10 bits [1], [2] depending on the size of the DAC elements. So as to achieve better linearity performance, one can utilize a DAC linearization techniques such as the Dynamic Element Matching (DEM) techniques [3], [4], component sorting [5], or component sizing method [6]. Both the sorting and sizing methods, however, increase silicon area due to the fact that the sorting method requires the registers to contain comparison results and demands complex routing, and that the sizing method calls for larger components as the required resolution increases higher.…”

“…It needs considerable amount of time to execute the algorithm and is inappropriate in high frequency operation since it should be performed in the time slot (non-overlap time of clock phases) between quantization and DAC operations. This timing problem is more critical in a highspeed continuous-time M as its operating frequency goes beyond half GHz [6]. Figs.…”