A 14-nm 0.14-ps<sub>rms</sub>Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Yao, Chunhua; Ni, Ronghua; Lau, C.E.; Wu, Wanghua; Godbole, Kunal; Zuo, Yongrong; Ko, Sangsoo; Kim, Nam-Seog; Han, Sang-Wook; Jo, Ikkyun; Lee, Joon‐Hee; Han, Juyoung; Kwon, Daehyeon; Kim, Chul‐Ho; Kim, Shinwoong; Son, Sang Won; Cho, Thomas Byunghak

doi:10.1109/jssc.2017.2742518

Cited by 54 publications

(12 citation statements)

References 15 publications

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“…TDC (Time to Digital Converter) is used to capture the phase information in practical design [10][11][12][13]. As shown in Figure 3, DFF (D flip-flop) is used as the delay cell, which has delayed time T to quantize the phase error.…”

Section: Design Of Simplified Charge Pump For Fast Locking Pllmentioning

confidence: 99%

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Guo

et al. 2021

Electronics

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.

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Section: Design Of Simplified Charge Pump For Fast Locking Pllmentioning

confidence: 99%

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Guo

et al. 2021

Electronics

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“…In traditional all digital PLLs, a complex and power-hungry time-to-digital converter (TDC) is needed for low jitter. However, in this system clock can tolerate relative large jitter and hence an TDCless or an embedded TDC similar to [12] using coarse timebase from multiple-phase VCO output and fine time-base from a phase interpolation block is used to save TDC calibration in gated-ring-oscillator (GRO) based TDC [13] or SAR based TDC [14] or frequency calibration (FCAL) and loop dynamic calibration needed in Bang-Bang ADPLLs [15].…”

Section: Low Power Frac-n All Digital Synthesizermentioning

confidence: 99%

A compact and low-power wireless receiver for implanted medical backscatter

Huo

Mao

Xie

et al. 2019

IEICE Electron. Express

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A compact and low-power wireless receiver supporting 2.4 GHz industrial, scientific and medical (ISM) band is implemented in a 130 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The GHz operating frequency renders the chip to be matched with a mm-sized antenna to reduce implants' size and improve patients' experience. To simplify the implanted chip, the downlink is through On-Off Keying (OOK) so non-coherent detection and simplified receiver chain can be deployed. Boosted Rectifier and open-loop amplifier-based receiver chain lowers the chip's power consumption to nW level. The measured sensitivity reaches −50 dBm at a Bit Error Rate (BER) of 1e-3.

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“…The concept of a piecewise-linear DPD is aimed to reduce the complexity of the DPD and make an adaptive implementation feasible. In the context of DPLLs, an adaptive piecewise-linear DPD was originally proposed in [14] and later employed in [15,16] for the correction of the digital-to-time converter (DTC) and time-to-digital converter (TDC) nonlinearity. The general idea of the piecewise linear DPD is illustrated in Fig.…”

Section: Adaptive Digital Pre-distortionmentioning

confidence: 99%

Chirp Generators for Millimeter-Wave FMCW Radars

Cherniak

Levantino

2019

Special Topics in Information Technology

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The vast number of radar applications generates the demand for highly-linear, low-noise, fast chirp generators implemented in nanoscale CMOS technologies. Off-the-shelf chirp synthesizers are realized in BiCMOS technologies and demonstrate excellent phase noise performances, though, at high cost and limited modulation speed. This chapter describes a new class of fast and reconfigurable chirp generators based on digital bang-bang phase-locked loops, suitable for integration in modern CMOS processes. After analyzing the impact of the chirp generator impairments on a frequency-modulated continuous-wave (FMCW) radar system, a novel pre-distortion scheme for the linearization of critical blocks is introduced to achieve at the same time low phase noise and fast linear chirps. The chirp generator fabricated in 65-nm CMOS technology demonstrates above-state-of-the-art performance: It is capable of generating chirps around 23-GHz with slopes up to 173 MHz/µs and idle times of less than 200 ns with no over or undershoot after an abrupt frequency step. The circuit consuming 19.7 mA exhibits a phase noise of −100 dBc/Hz at 1 MHz offset from the carrier and a worst case in-band fractional spur level below −58 dBc. Keywords CMOS • Phase-locked loops • Radar 3.1 Introduction Cost reduction is the cornerstone in nowadays radar systems. The radar technology, which has been for a long time, since the invention in early 1930s, exclusive to military and defence, is now being adopted in a wide spectrum of applications This work has been supported by Infineon Technologies, Austria.

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A 14-nm 0.14-ps_rmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Cited by 54 publications

References 15 publications

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

A compact and low-power wireless receiver for implanted medical backscatter

Chirp Generators for Millimeter-Wave FMCW Radars

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A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Cited by 54 publications

References 15 publications

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

A compact and low-power wireless receiver for implanted medical backscatter

Chirp Generators for Millimeter-Wave FMCW Radars

Contact Info

Product

Resources

About

A 14-nm 0.14-ps_rmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration