A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-<i>N</i> Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS

Chen, Yan-Ting; Peng, Pen-Jui; Lin, Hung Wen

doi:10.1109/tvlsi.2022.3160327

Cited by 6 publications

(3 citation statements)

References 22 publications

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“…Several PIs have been reported before such as in [8][9][10][22][23][24]. Some of them use multi-phase clocks for phase interpolation.…”

Section: Circuit Design Of the Phase Interpolator With Immunity To Pv...mentioning

confidence: 99%

“…That means a significant amount of time and financial investment are required. Another choice is to replace Int-N PLLs with fractional-N PLLs (Frac-N PLLs) like in [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16], multiplying reference frequency with fractional value. Within this choice, we have a few options: acquiring Frac-N PLLs from a silicon IP developer or developing the necessary PLLs from scratch.…”

Section: Introductionmentioning

confidence: 99%

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Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Motozawa,

Hiraku,

Hirai

et al. 2023

Electronics

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In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

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“…Several PIs have been reported before such as in [8][9][10][22][23][24]. Some of them use multi-phase clocks for phase interpolation.…”

Section: Circuit Design Of the Phase Interpolator With Immunity To Pv...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Motozawa,

Hiraku,

Hirai

et al. 2023

Electronics

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show abstract

“…The original publication, [8], presented a multi-rate design that operates at a speed of up to 3GHz. Therefore, a multi-rate design can be explored with a much wider band of frequencies such as the designs described in [28] and [29], or a multi-rate design at much higher speeds such as the phase interpolator described in [30].…”

Section: Discussionmentioning

confidence: 99%

All Digital CMOS 5-BIT Phase Interpolator at 10 Gigahertz in 65NM Technology

Kooner

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Phase interpolators are critical blocks in some clock and data recovery (CDR) systems.These interpolators are generally implemented using current-mode logic (CML). This work presents the design of an all-digital phase interpolator based on static CMOS logic gates and cells with a 5-bit resolution. This phase interpolator demonstrates functionality with input clock frequencies of 10 GHz while maintaining relatively low power consumption and acceptable linearity. The interpolator as a standalone block was characterized through post-layout simulations using extracted parasitics and simulating across process, voltage, and temperature (PVT) variations. This design achieves a worstcase power consumption of 6.7mW, DNL of 0.26 LSB, INL of 0.31 LSB, and a settling time of 4 clock cycles. This phase interpolator was partially fabricated as a component of a system. The system was fabricated in the TSMC 65nm general-purpose technology and process.

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Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications

Ahirwar,

Shankhwar,

Kaushal

et al. 2022

2022 IEEE Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI)

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A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS

Cited by 6 publications

References 22 publications

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

All Digital CMOS 5-BIT Phase Interpolator at 10 Gigahertz in 65NM Technology

Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications

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