1992
DOI: 10.1109/23.159682
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A 1006 element hybrid silicon pixel detector with strobed binary output

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Cited by 91 publications
(27 citation statements)
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“…The chip was again manufactured in the SACMOS3 technology, and after bump-bond assembly at GEC-Marconi in Caswell, the first particle tracks were measured at CERN on 20 October 1991. These measurements were presented at the 1991 Nuclear Science Symposium in Santa Fe [16], two years after those of the first chip. In the scientific community, with relatively modest resources long iteration times are typical, also because the design teams are involved in the development and testing of the full application system.…”
Section: The Earliest 'Micropattern' Pixel Detectorsmentioning
confidence: 99%
“…The chip was again manufactured in the SACMOS3 technology, and after bump-bond assembly at GEC-Marconi in Caswell, the first particle tracks were measured at CERN on 20 October 1991. These measurements were presented at the 1991 Nuclear Science Symposium in Santa Fe [16], two years after those of the first chip. In the scientific community, with relatively modest resources long iteration times are typical, also because the design teams are involved in the development and testing of the full application system.…”
Section: The Earliest 'Micropattern' Pixel Detectorsmentioning
confidence: 99%
“…This photocathode is at 30 mm distance viewed by a 8 mm × 4.8 mm area silicon chip #3 , containing 1024 pixels of 75 µm × 500 µm size #4 . Each pixel is bump-bonded to its individual front-end electronics, composed of preamplifier, comparator, delay line, coincidence logic and memory element, providing a binary response to the photoelectrons [3,4] #5 . The pixels are readout in a parallel line mode #6 .…”
Section: Introductionmentioning
confidence: 99%
“…A striking example of the use of combined semiconductor technologies is the hybrid pixel detector. It has been possible ~1990 to achieve integration of a true 2-dimensional (2D) sensor matrix of microscopically segmented silicon elements and a matching matrix of CMOS readout electronics [1]. Due to the miniaturization of the electrical capacitances the thousands of parallel amplifiers in such an integrated circuit achieve low noise (~100 e -rms) signal processing with ns precision for asynchronous MHz pulse rates.…”
Section: Semiconductor Technology and Physicsmentioning
confidence: 99%