A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter

A 4-port-inductor-based VCO coupling method for phase noise reduction

“…On the other hand, the improvement of the CCVCO design is 8 Finally, the performance of the three VCO designs are summarized in Table I and compared with two previously published designs. [3] uses a similar technology but higher voltage supply and [4] uses a better technology but the same voltage supply as our prototypes. Both proposed CVCO topologies have achieved lower phase noise than the reference design (NVCO).…”

A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application

“…Larger feedback resistor also reduces the input referred noise and the trade-off here is the bandwidth is reduced. The gain transfer function of the design is given by (2). Input capacitance, C pd and series spiral inductor, L S is under complex formulation which will be resonated at high frequencies to eliminate the effect of bandwidth degradation and results in bandwidth extension.…”

“…Such system is well achieved through the implementation of fiber optic transmission over a copper medium. In the past, many papers with the optical receiver operated at 10-Gb/s in CMOS process were published [1][2][3][4][5][6][7][8][9]. Only few were fabricated in 0.18-µm CMOS technology [4][5][6][7][8][9].…”

A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops

“…It must extract clock information from the received data and retime data by the extracted clock. The CDR circuits commonly use dual loops [1][2][3][4]: a frequency detector (FD) based frequency acquisition loop locked to a reference clock to bring the voltagecontrolled oscillator (VCO) frequency close to the desired data rate, and a phase detector (PD) based phase tracking loop locked to the incoming data for clock recovery. However, the reference clock may not be readily available in applications such as a data repeater.…”