A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

Chen, Wei-Zen; Cheng, Ying-Lien; Lin, Da-Shin

doi:10.1109/jssc.2005.845970

Cited by 98 publications

(7 citation statements)

References 9 publications

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“…However, the intrinsic cascode configuration limits its bandwidth if supply voltage is not high enough. In most cases, passive matching or peaking techniques are adopted, such as capacitive, inductive, and transformer peaking [1,2,[5][6][7][8][9][10]33], which are at the expense of voltage headroom and area consumption. An active inductor, as an alternative, may occupy less area than an on-chip inductor, but corrupt noise performance severely [11,18].…”

Section: Feed-forward Common Gate Input Stage Design Within Power Conmentioning

confidence: 99%

Low‐power, low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

Wang

2011

Circuit Theory & Apps

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SUMMARYA novel circuit technique was applied to the design of a preamplifier for ultra high-speed short-distance parallel optical communication system in standard 180-nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low-cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed-forward common gate stage to achieve high gain bandwidth product under limited f T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain-boosting stages are adopted, which makes the design simple and favorable in low-cost high-density multi-channel optical communication system. The preamplifier provides a transimpedance gain of up to 52dBΩ and a 3-dB bandwidth of 8.4GHz. Operating under a 1.8-V supply, the power dissipation is 8mW, and the chip area is only 0.075Â0.08mm. The measured average input-referred noise-current spectral density is 27 pA= ffiffiffiffiffiffi Hz p .

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Section: Feed-forward Common Gate Input Stage Design Within Power Conmentioning

confidence: 99%

Low‐power, low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

Wang

2011

Circuit Theory & Apps

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“…It is embarrassed that the transimpedance gain and the output pole frequency of these TIAs are both dependent on the resistor, which makes it hard to make tradeoff between gain and bandwidth for designers. In addition, the excess area occupied makes it prohibitive to adopt inductive peaking technique for low-cost applications [24][25][26]. And the inductorless bandwidth extension techniques, such as active feedback and negative capacitance compensation are also commonly used in the design of the high-speed Rx_AFE [27][28][29].…”

Section: Introductionmentioning

confidence: 99%

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

Zhou

Mao

Xie

et al. 2021

IEICE Electron. Express

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In this paper, a 30 Gbps 1.25 pJ/b optical receiver analog front-end (Rx_AFE) mainly consisting of an active voltage-current feedback transimpedance amplifier (AVCF-TIA) and a staggered active feedback limiting amplifier (LA) is presented. By adopting active voltage-current feedback technique in the proposed TIA, the large input capacitance is well-isolated without the limitation of low supply voltage, and the direct contradiction between transimpedance gain and output pole frequency is alleviated significantly. Meanwhile, the bandwidth is further extended by adopting staggered active feedback technique in the LA designing. Fabricated in a 40 nm bulk-CMOS technology, the presented Rx_AFE exhibits a transimpedance gain of 63.8 dBΩ and a 3-dB bandwidth of 24.3 GHz. From supply voltage of 1.0 V, power dissipation and power efficiency of the circuit are 37.5 mW and 1.25 pJ/b respectively, when 30 Gbps PRBS is operated. The core circuit occupies a chip area of 920 µm × 690 µm.

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“…Furthermore, a high-speed CMOS trans impedance amplifier (TIA) and a limiting amplifier (LA) are available and can be monolithically integrated with Si-PD in a CMOS-compatible process to achieve an all-Si optical receiver. [10][11][12][13][14][15] There have been several reports on the study of CMOScompatible Si-PDs in recent years. [16][17][18] However, as a common issue, due to the fact that the light penetration depth of Si at 850 nm is more than 10 µm, carriers generated from the bulk Si substrate diffuse slowly and are collected, significantly affecting the response performance and limiting the resulting bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

Maekita

Mitsuno

et al. 2015

Jpn. J. Appl. Phys.

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We report a design and implementation of lateral silicon photodetectors fabricated on a silicon-on-insulator (SOI) substrate in a complementary CMOS-compatible process. In addition, we disscuss the structure dependences on the frequency and optimum design for a maximum bandwidth. A standard device fabricated with a 210 nm absorbing layer, a finger width of 1.00 µm, a finger spacing of 1.63 µm, a square detector area of 20 × 20 µm2, and a pad size of 60 × 60 µm2 achieved a bandwidth of 12.6 GHz at a bias voltage of 10 V, with a responsivity of 7.5 mA/W at 850 nm wavelength. A photodetector with the same geometry, which was fabricated with a smaller pad size of 30 × 30 µm2, exhibited a bandwidth of 13.6 GHz.

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A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

Cited by 98 publications

References 9 publications

Low‐power, low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

Low‐power, low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

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