A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

Dohar, Suraj Singh; Rajan, Siddharth; Vasantha, M. H.; Kumar, Yogesh

doi:10.1109/ted.2021.3064899

Cited by 17 publications

(7 citation statements)

References 15 publications

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“…The write access time is defined as the time interval between two points, starting from the WL turn-on time and ending when the storage node voltage rises (or falls) to 50% of the supply voltage (supply voltage is 1.2 V). 16 In Figure 7A, the memory cells SCCS-18 T and NASA-13 T have the fastest write speeds, with the former using six transistors to write data and the latter using a read/write separation design pattern to reduce current competition during writing. The cell proposed in this paper enhances the current competition between nodes due to the use of a polarity-reinforced radiation-hardened design for the storage nodes.…”

Section: Read Access Time and Write Access Timementioning

confidence: 99%

“…The read access time is defined as the time interval between the two points after the pre‐charging of the two bit‐lines has been completed (both BL and BLB are above 600 mv), starting from the WL turn‐on time and ending with a difference of 50mv between the voltages of the two bit‐lines. The write access time is defined as the time interval between two points, starting from the WL turn‐on time and ending when the storage node voltage rises (or falls) to 50% of the supply voltage (supply voltage is 1.2 V) 16 …”

Section: Simulation Analysis and Comparisonmentioning

confidence: 99%

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Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Bai,

Chen,

et al. 2023

Circuit Theory & Apps

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SummaryAs the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations.

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Section: Read Access Time and Write Access Timementioning

confidence: 99%

Section: Simulation Analysis and Comparisonmentioning

confidence: 99%

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Bai,

Chen,

et al. 2023

Circuit Theory & Apps

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“…However, none of them have high Q crit . An RHBD 10T SRAM cell proposed in [80] provides full SEU immunity and can recover from both 0→1 and 1→0 SEUs on any one of its nodes. Their proposed design is also acceptable with respect to area.…”

Section: ) Previous Cell Designs That Cannot Provide Seu Tolerancementioning

confidence: 99%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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“…Generally, high resistivity of the materials can be achieved through two different techniques such as (i) eliminating the background impurities [10] and (ii) introducing the compensated acceptors. In previous reports, iron (Fe) [11,12] and carbon (C) [13][14][15][16][17][18][19][20] atoms are used as a compensator. Besides, the generation of intentionally edge dislocation in GaN [21,22] are also used as a compensator.…”

Section: Introductionmentioning

confidence: 99%

Understanding of impact of carbon doping on background carrier conduction in GaN*

Liu¹,

Li²,

Zhang³

et al. 2021

Chinese Phys. B

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The impact of carbon doping on the background carrier conduction in GaN has been investigated. It is found that the incorporation of carbon can effectively suppress the n-type background carrier concentration as expected. Moreover, from the fitting of the temperature-dependent carrier concentration and mobility, it is observed that high nitrogen-vacancy (V N ) dominates the background carrier at room temperature which consequently results in n-type conduction. The doping agent (carbon atom) occupies the nitrogen site of GaN and forms C N deep acceptor as revealed from photoluminescence. Besides, a relatively low hole concentration is ionized at room temperature which was insufficient for the compensation of n-type background carriers. Therefore, we concluded that this background carrier concentration can be suppressed by carbon doping, which substitutes the N site of GaN and finally decreases the V N .

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A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

Cited by 17 publications

References 15 publications

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Understanding of impact of carbon doping on background carrier conduction in GaN*

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