A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

Kanaya, Haruichi; Tomioka, K.; Matsushita, T.; Omura, Mitsuhiro; Ozaki, T.; Kumura, Y.; Shimojo, Y.; Morimoto, T.; Hidaka, O.; Shuto, S.; Koyama, Hiroshi; Yamada, Yuki; Osari, Kazutomo; Tokoh, N.; Fujisaki, F.; Iwabuchi, N.; Yamaguchi, Naoya; Watanabe, T.; Yabuki, Masanori; Shinomiya, Hiroshi; Watanabe, Naoya; Itoh, E.; Tsuchiya, Takao; Yamaguchi, Koji; Natori, Kenji; Yamazaki, S.; Nakazawa, Kimitaka; Takashima, D.; Shiratake, S.; Ohtsuki, Satoshi; Oowaki, Y.; Kunishima, I.; Nitayama, A.

doi:10.1109/vlsit.2004.1345446

Cited by 12 publications

(4 citation statements)

References 2 publications

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“…Although the NAND-like structure has a theoretically 4F 2 cell size but the ferroelectric capacitors require contacts in each cell to connect and that enlarges the cell. A nestled chain structure [36] that shares the bottom electrode for two cells was proposed to reduce the cell size by ∼32%. An advanced nestled chain structure further increases the density by an efficient geographic arrangement has recently been reported [37].…”

Section: Ferroelectric Memory (Feram)mentioning

confidence: 99%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

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Section: Ferroelectric Memory (Feram)mentioning

confidence: 99%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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“…7 shows a state-of-theart FeRAM cell used in 64 Mb FeRAM with a cell size of 0.602 lm 2 . Key technologies are the nestled chain cell structure and one-mask etching process of ferroelectric capacitors [14]. In chain FeRAM structure, a pair of capacitors is electrically connected to a same node.…”

Section: Ferammentioning

confidence: 99%

Advanced memory concepts for DRAM and nonvolatile memories

Horiguchi

2006

Solid-State Electronics

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“…Intense efforts are underway to commercialize high density FRAM technology. [5][6][7][8][9][10][11][12] In this article, we report on the bit distribution and reliability characteristics of high density ferroelectric memory arrays embedded within a 130 nm standard complementary metal oxide semiconductor (CMOS) logic process, operable at 1.5 V, with 5 lm copper/fluorosilicate glass (FSG) back end. We describe the device features of the different technology nodes up to the 65 nm node, and then delineate the process steps involved in integrating the FRAM module into a standard CMOS logic.…”

Section: Introductionmentioning

confidence: 99%

Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

Udayakumar¹,

Boku²,

Remack³

et al. 2006

jjap

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High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 mm 2 (130 nm node) to 0.15 mm 2 ($65 nm node). Wide signal margins, stable retention ()10 years at 85 C), and high endurance read/write cycling ()10 12 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.

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A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

Cited by 12 publications

References 2 publications

State-of-the-art flash memory devices and post-flash emerging memories

State-of-the-art flash memory devices and post-flash emerging memories

Advanced memory concepts for DRAM and nonvolatile memories

Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

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