A 0.35 μm SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

Decoutere, Stefaan; Vleugels, F.; Kuhn, R.; Loo, Roger; Caymax, Matty; Jenei, S.; Croon, J.A.; Huylenbroeck, Stefaan Van; Rold, M. Da; Rosseel, Eveline; Chevalier, P.; Coppens, P.

doi:10.1109/bipol.2000.886184

Cited by 7 publications

(7 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Currently, chip manufacturers focus mainly on the integration of Si 1Ϫx Ge x in heterojunction bipolar transistors ͑HBT͒ in Bi complementary metal oxide semiconductor ͑BiCMOS͒ technology. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] In a next phase, attention goes to the fabrication of Si/Si 1Ϫx Ge x heterojunction CMOS devices to improve the performance of the p-type metal oxide semiconductor ͑MOS͒ device, [16][17][18][19][20][21][22][23][24] and to elevated Si 1Ϫx Ge x source/drain contacts to reduce short channel effects in CMOS technology. [25][26][27][28][29] For the first two applications, both selective and nonselective epitaxial growth by means of chemical vapor deposition ͑CVD͒ can be used.…”

mentioning

confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

Self Cite

View full text Add to dashboard Cite

Si 1Ϫx Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1Ϫx Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity ͑microloading on a micrometer scale and gas depletion on a wafer scale͒ and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1Ϫx Ge x growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content ͑no microloading͒ and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (ϳ2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of Si 1Ϫx Ge x heterojunction bipolar transistors ͑0.35 and 0.25 m technology͒, and p-type Si 1Ϫx Ge x heterojunction metal oxide semiconductor devices ͑effective gate length down to 70 nm͒.

show abstract

mentioning

confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Among the first exciting results with this architecture, we note the work of NEC [30] and Siemens [31]. More recent work has been published by Hitachi [32], Infineon [33] and IMEC [34]. A typical process cross section of a selective SiGe HBT is shown in figure 4.…”

Section: Selective Sige Growthmentioning

confidence: 99%

SiGe HBT for application in BiCMOS technology: II. Design, technology and performance

Jain

Decoutere

Willander

et al. 2001

Semicond. Sci. Technol.

View full text Add to dashboard Cite

SiGe technology has acquired great importance in recent years. Recent advances made in the SiGe HBT technology for analogue applications are discussed in this two-part review paper. Strain, stability, reliability, mobility of charge carriers, bandgap narrowing and effective density of states of SiGe layers have been discussed in part I. This paper (part II) is devoted to the HBTs: their design and performance. The two designs of the HBTs developed by IBM and by Daimler-Benz are discussed. Their relative merits and constraints imposed by the stability criterion on each design are described. The technology used for implementing the two designs is also described. The dc and ac characteristics and Ge profiles needed to optimize different figures of merit are discussed in detail. The parasitic barriers created by outdiffusion of B and also on operating the HBT at high current densities are explained. High injection barriers can be suppressed by a special design of the Ge profiles. Introduction of C in the base suppresses outdiffusion of B. HBTs with SiGeC base layers are discussed. Issues involved in simultaneous optimization of f T , f max and BV CEO are addressed. Values of f T , f max and BV CEO of high-performance HBTs are compiled and given in a table. The noise characteristics of the SiGe HBTs are far superior to those of III-V devices. Noise in SiGe HBTs is discussed in detail. Finally, a summary of selected circuits that have been fabricated using SiGe HBTs is given.

show abstract

“…The metal-insulator-metal (MIM) capacitors in silicon mixed-signal and radio-frequency IC applications have attracted great attention owing to their high-conductivity electrodes and low parasitic capacitance. [1][2][3] In general, silicon oxide and silicon nitride are used as dielectrics in conventional MIM capacitors. [4][5][6] Although these dielectrics can provide good voltage linearity properties and low temperature coefficients, their capacitance density is limited because of low dielectric constants (3.9 for SiO 2 , 7 for Si 3 N 4 ).…”

Section: Introductionmentioning

confidence: 99%

Effect of Thermal Annealing or Plasma Treatment on Analog Characteristics for High-k Material Capacitors

Kang¹,

Chen²,

Lin³

et al. 2008

jjap

View full text Add to dashboard Cite

For TaN/HfO 2 /TaN capacitors, thermal annealing or plasma treatment is conducted after HfO 2 deposition. Rapid thermal annealing or furnace thermal annealing at 400 C can improve the leakage current but worsens the voltage linearity of capacitance. A capacitor with adequate NH 3 plasma treatment can have a lower leakage current and a better voltage linearity property compared with the control sample. Atomic force microscopy (AFM) data indicate that the roughness of thermalannealed or plasma-treated HfO 2 film is related to the voltage linearity property for the capacitor. In addition to thermally induced stress, the oxygen atoms diffuse through the HfO 2 film and then oxidize the bottom TaN electrode, leading to a rougher interface during O 2 thermal annealing. Because of nitrogen atom diffusion into HfO 2 film and a less damaged surface, the quality of the TaN/HfO 2 interface and HfO 2 film can be improved, which leads to better analog characteristics.

show abstract

A 0.35 μm SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

Cited by 7 publications

References 3 publications

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

SiGe HBT for application in BiCMOS technology: II. Design, technology and performance

Effect of Thermal Annealing or Plasma Treatment on Analog Characteristics for High-k Material Capacitors

Contact Info

Product

Resources

About