80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Viraraghavan, Janakiraman; Leu, Derek; Jayaraman, Balaji; Cestero, Alberto; Kilker, Robert; Golz, John; Tummuru, Rajesh R.; Raghavan, Ramesh; Moy, D.; Kempanna, Thejas; Khan, Faraz A.; Kirihata, T.; Iyer, S. Sundar Kumar

doi:10.1109/vlsic.2016.7573462

Cited by 12 publications

(8 citation statements)

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“…5 shows bitmaps of a CTT memory array fabricated in 14nm FinFET production technology. Details about circuit design and sensing techniques implemented in this technology have been discussed elsewhere [12].…”

Section: Program and Erase Optimization And Cyclingmentioning

confidence: 99%

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Khan

Cartier

Woo

et al. 2017

IEEE Electron Device Lett.

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The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated highk-metal-gate logic devices, we introduce a unique multipletime programmable embedded non-volatile memory element, called the 'charge trap transistor' (CTT), for high-kmetal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density (∼0.144µm 2 /bit for 22 nm and ∼0.082µm 2 /bit for 14 nm technology), logic voltage compatible and low peak power operation (∼4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks. Index Terms-High-k-metal-gate, CMOS, embedded non-volatile memory. I. INTRODUCTION T HERE is an ever-increasing need for on-chip memory in VLSI technologies. In this letter, we demonstrate the application of HfO 2 based high-k-metal-gate (HKMG) logic devices, called 'Charge Trap Transistors' (CTTs), as nonvolatile memory (NVM) elements for system-on-chip (SoC) applications in state-of-the-art CMOS technologies. Recently, we demonstrated that intrinsic self-heating enhanced charge trapping in HKMG devices can be used to achieve large and stable device threshold voltage (V T) shifts that are suitable Manuscript

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Section: Program and Erase Optimization And Cyclingmentioning

confidence: 99%

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Khan

Cartier

Woo

et al. 2017

IEEE Electron Device Lett.

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“…However bypassing local circuitry on a functional die by communicating with a UD should only be done in extreme cases. At the system level, The UDs can store information regarding the functionality of other UDs and functional dies in embedded nonvolatile memory, such as OTPM/MTPM [17]. A certain die can fail either during processing (fabrication and bonding) or during operation.…”

Section: Redundancy Allocationmentioning

confidence: 99%

Network on interconnect fabric

Vaisband¹,

Bajwa²,

Iyer³

2018

2018 19th International Symposium on Quality Electronic Design (ISQED)

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Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 µm) horizontal and vertical interconnects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.

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“…Recently, CTTs were proven as digital memory devices in [6] and [8] with error-proof trapping and detrapping algorithms, and more interestingly, it was used to execute unsupervised learning computation in [9] and [10]. In our previous work [11], a 784 × 784 CTT-based analog computing engine was proposed.…”

Section: Introductionmentioning

confidence: 99%

Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

Fan

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage (V TH ). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50-and 100-mV continuous V TH tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.INDEX TERMS Analog arithmetic unit (AAU), charge trapping/detrapping, charge-trap transistor (CTT), nonvolatile memory (NVM), programmable threshold voltage.

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80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Cited by 12 publications

References 0 publications

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Network on interconnect fabric

Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

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