70 input, 20 nanosecond pattern classifier

Abstract

Abstmcf -A CMOS neural network integrated circuit is discussed, which was designed for very high speed applications. This full-custom, mixed analog-digital chip implements a fully connected feedforward neural network with 70 inputs, 6 hidden layer neurons and one output neuron. The neurons perform inner product operation and have sigmoid-like activation function. The 70 network inputs and the neural signal processing are analog, the synaptic weights are digitally programmable with 5 bit (4 bits + sign) precision.The synaptic weights are stored on onchip static R A M cells. The combination of analog and digital techniques results Unique computing power with ease of use. Progrrunming can easily be performed with the help of a spreadsheet or other suitable Interface program from a PC. The resolution of the input signals is mainly determined by the signal to noise ratio which lies typically between 8-12 bits. Therefore the equivalent Input bandwidth can be as high as 28-42 GbiWsecond. The system is designed for very high speed vector classification and the feasibility of a Single chlp neural network photon trigger for nudear research is shown. Because of the fully parallel architecture and the fast analog signal processing the network achieves unique computing performance and clasdfles up to 70 dimensional vectors within 20 nanoseconds, performing 20 billion (2*1010) multiply-and-add operations per second. The circuit occupies l0r9mm2 silicon area with 1.5p.m CMOS process and Bissip8tes only 1W at SV supply.

A neural-network architecture for syntax analysis

“…BMP architecture with two layers of connection weights is same as that implemented by [50] except that the latter uses integer input values, 5-bit synaptic weights, one output neuron, and sigmoid-like activation function whereas BMP uses binary input values, synaptic weights from multiple output neurons, and binary hardlimiter as activation function. Hence the computation delay of BMP module implemented using current CMOS technology can be expected to be at best of the order of 20 ns.…”

Neural architectures for database query processing, syntax analysis, knowledge representation, and inference

“…reports a measured propagation delay of 104ns in a digital circuit with each synapse containing an 8-bit memory, an 8-bit subtractor and an 8-bit adder [50]. reports throughput at the rate of lOMHz (or equivalently, delay of 100ns) in a Hamming Net pattern classifier using analog circuits [106]. describes a hybrid analog-digital design with 5-bit (4 bits -f-sign) binary synapse weight values and current-summing circuits that is used to realize a 2-layer feed-forward ANN with a network computation delay of less than 20ns.The Ist-layer and 2nd-layer subnetworks of the proposed neural architecture for database query processing are very similar to the Ist-layer subnetwork of a Hamming Net respectively, and the neural architecture with 2 connection layers in the proposed ANN is exactly same as that implemented by[106] except[106] uses discretized inputs, 5-bit synaptic weights, and 1} and binary hardlimiter as activation function.…”