DOI: 10.7591/9780801468926-011
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Abstract: This paper presents a new hardware-software co-design methodology for resource constrained SoC realized in a deep submicron process (DSM). The methodology is useful for multimedia applications optimized for latency. The approach addresses layout and hardware aspects relevant to system design: it considers the dependency of task communication speed on interconnect parasitic, as well as the possibility of sharing coarse and medium grained IP cores across tasks. The methodology includes an original algorithm for …

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