THIS PAPER WILL DESCRIBE a +5V only 32K EEPROM which implements a page load mode. The part is fabricated with an Isolated N-channel Silicon-Nitride-Oxide-Silicon (ISO-SNOS) process. The part uses 3508 of silicon nitride in addition to a thin oxide to form the memory transistor. Such a structure reduces the probability of pinholes, allowing the memory transistor to use generous layout rules, yet resulting in a cell that is only0.39mi12. This is in contrast to many of the earlier EEPROMs which rely on two condu…
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