Untitled

Shackleford, Barry; Snider, Greg; Carter, Richard J.; Okushi, Etsuko; Yasuda, Mitsuhiro; Seo, Katsuhiko; Yasuura, Hiroto

doi:10.1023/a:1010018632078

Cited by 65 publications

(2 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several FPGA-based implementations of evolutionary algorithms have been presented in the literature to accelerate the optimization process. Most of these approaches focus on the optimal design of hardware accelerators to achieve high performance and flexibility [25,26] and satisfy other genetic algorithm features, such as multi-objective optimization [27]. In our approach, we adopted the BB-BC optimization algorithm due to its low computational time and high global convergence speed.…”

Section: Bb-bc Algorithm In Fpgamentioning

confidence: 99%

Fast Tuning of the PID Controller in An HVAC System Using the Big Bang–Big Crunch Algorithm and FPGA Technology

2018

View full text Add to dashboard Cite

This article presents a novel technique for the fast tuning of the parameters of the proportional–integral–derivative (PID) controller of a second-order heat, ventilation, and air conditioning (HVAC) system. The HVAC systems vary greatly in size, control functions and the amount of consumed energy. The optimal design and power efficiency of an HVAC system depend on how fast the integrated controller, e.g., PID controller, is adapted in the changes of the environmental conditions. In this paper, to achieve high tuning speed, we rely on a fast convergence evolution algorithm, called Big Bang–Big Crunch (BB–BC). The BB–BC algorithm is implemented, along with the PID controller, in an FPGA device, in order to further accelerate of the optimization process. The FPGA-in-the-loop (FIL) technique is used to connect the FPGA board (i.e., the PID and BB–BC subsystems) with the plant (i.e., MATLAB/Simulink models of HVAC) in order to emulate and evaluate the entire system. The experimental results demonstrate the efficiency of the proposed technique in terms of optimization accuracy and convergence speed compared with other optimization approaches for the tuning of the PID parameters: sw implementation of the BB–BC, genetic algorithm (GA), and particle swarm optimization (PSO).

show abstract

Section: Bb-bc Algorithm In Fpgamentioning

confidence: 99%

Fast Tuning of the PID Controller in An HVAC System Using the Big Bang–Big Crunch Algorithm and FPGA Technology

2018

View full text Add to dashboard Cite

show abstract

“…Hardware implementation of a genetic algorithm with its application in the synthesis of logic circuits has been developed by Shackleford (2001). The paper itself does not produce an evolutionary structure within the meaning of hardware reconfiguration was classified here as an example of application in the synthesis of logic circuits of hardware genetic algorithms.…”

Section: Synthesis Of Logic Circuits Using Evolutionary Algorithmsmentioning

confidence: 99%

Intrinsic Evolvable Hardware Used for Fault Tolerance Systems

Ionescu

Mazăre

Șerban

2012

International Journal of Organizational and Collective Intelligence

View full text Add to dashboard Cite

The main target of this chapter is to present the intrinsic evolvable hardware structures: concept, design and applications. The intrinsic evolvable hardware structures concept join more research areas like: bio – inspired searching methods (evolutionary algorithms), optimization of algorithms by parallel processing and reconfigurable circuits. First, a general overview about intrinsic evolvable hardware structure is presented. The intrinsic evolvable hardware structure consists in two main modules: hardware genetic algorithm and dynamic reconfigurable circuit. In a particular application, the hardware genetic algorithm searches the configuration that makes the reconfigurable circuit to correctly respond to application requirements. In a background section are presented the genetic algorithm concept as a bio-inspired search solution, the hardware reconfiguration concept with sub areas classifications and the research directions in the evolvable hardware structures areas with application examples. In the first part of the main section are presented the design solutions for hardware implementation of genetic algorithm. Then the solutions are presented for the reconfigurable circuit design and interconnection between reconfigurable circuit and hardware genetic algorithm. Finally, are presented several applications that illustrate the usefulness of the intrinsic evolvable hardware structure. Intrinsic evolvable hardware can be used as a method of resolving faults occurring in some parts of the digital circuit.

show abstract

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Glette

Tørresen

2005

Evolvable Systems: From Biology to Hardware

View full text Add to dashboard Cite

Untitled

Cited by 65 publications

References 23 publications

Fast Tuning of the PID Controller in An HVAC System Using the Big Bang–Big Crunch Algorithm and FPGA Technology

Fast Tuning of the PID Controller in An HVAC System Using the Big Bang–Big Crunch Algorithm and FPGA Technology

Intrinsic Evolvable Hardware Used for Fault Tolerance Systems

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Contact Info

Product

Resources

About