400-MHz frequency counter

Abstract

This poster describes the implementation of a 400-MHz frequency counter in an XC4002XL FPGA. In addition to speed, other objectives were low power and efficient resource utilization. These objectives were met using a semisynchronous design technique where pairs of flip-flops operate as synchronous state machines that are cascaded asynchronously. XC4OOOXL CLBs each contain two flip-flops that share a common clock input. This common clock permits the pair of flip-flops to operate synchronously in spite of clock routing on local interconnect. A fully asynchronous design would waste half of the flip-flops since there would be no individual clock access. The outcome of the project was a full-featured frequency counter that operates at 400 MHz, consumes only 130 mW at the maximum input frequency, and occupies 56 CLBs, less than 90% of an XC4002XL.This work studies some architectural characteristics of mixed signals FPGAs. The effect of programmability through the use of switches is analyzed, and it is shown that the result is a transfer function modification when real characteristics of the switches are assumed. Moreover, the paper proposes the use of externally linear, internally nonlinear analog circuits, since this procedure could eliminate the error introduced by the switches. Using this approach, analog area is greatly reduced, and circuits can be built on top of completely digital technologies. Some experimental results in the analog and digital domain support the proposed approach to mixed circuits reprogrammability, being the basis for a mixed signal FPGA.ATLANTIS is the result of 5 years experience with large stand-alone and smaller PC1 based FPGA processors. It realizes a hybrid system with a close coupling of RISC and FPGAs. Current applications are pattern recognition in high energy physics (HEP), image processing and n-body calculation. CompactPCI provides the basic communication mechanism. Dedicated FPGA boards for computing and I/O plus a private backplane for up to 1 GB/s data rate support flexibility and scalability. FPGAs with over 200k gates and 400 I/O pins are used. The I/O board with 2 FPGAs is configurable via mezzanines allowing up to 8 channels of lOOMB/s. The computing board with 4 FPGAs has a fixed architecture but a flexible memory system by using submodules. For HEP e.g. a total of 40MB SRAM with 4.5 GB/s bandwidth is used. The high-performance hardware is complemented by CHDL, a FPGA design tool with special support for hybrid systems.