2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE) 2019
DOI: 10.23919/date.2019.8715080
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2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection

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Cited by 58 publications
(17 citation statements)
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“…The HPC registers are responsible to collect a myriad of low-level events such as cache access and misses, TLB hits and misses, branch mispredictions, etc. [18,22,30].…”
Section: Hardware Performance Countersmentioning
confidence: 99%
See 4 more Smart Citations
“…The HPC registers are responsible to collect a myriad of low-level events such as cache access and misses, TLB hits and misses, branch mispredictions, etc. [18,22,30].…”
Section: Hardware Performance Countersmentioning
confidence: 99%
“…Performance counter registers are easily programmable across all platforms. Depending on the processor architecture, there are different numbers of HPC registers available [18,22,30]. For instance, the number of counter registers in the Intel Ivy-bridge and Intel Broadwell CPUs is limited to only four per processor core, meaning that only four HPCs can be captured simultaneously.…”
Section: Hardware Performance Countersmentioning
confidence: 99%
See 3 more Smart Citations