23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers

Low-Power 56Gb/s NRZ Microring Modulator Driver in 28nm FDSOI CMOS

“…With a calculated IL of −11 dB, an assumed 10 dBm laser power and 5 dB loss due to edge couplers and waveguides, we calculate an optical modulation amplitude (OMA) of −6 dBm. This OMA is 4 dB above the −10 dBm required by state-ofthe-art receivers to achieve a BER ≤ 1·10 −12 with an assumed photodiode responsivity of 0.8 A/W [9]. Moreover, this margin increases from 4 dB to 7 dB when using KP-FEC (2 · 10 −4 ).…”

Coherent ePIC Receiver for 64 GBaud QPSK in 0.25 μm Photonic BiCMOS Technology

“…To avoid this potential instability, the feedback path (Q f1 and Q f2 ) and the output driver path (Q O1 and Q O2 ) are separated into two parallel EF stages [9]. To further improve the bandwidth of the circuit, while keeping acceptable group delay variation and stability, other peaking techniques were also investigated: cascode stage, inductive peaking, negative Miller Capacitance compensation [11], negative capacitance circuit [12]. Cascode amplifier was not used in the TIA stage to keep the input dynamic voltage range high, so that the input amplifier could accommodate a wide range of input signal powers without the necessity to precisely control the feedback loop.…”

“…Table I compares coherent receivers in similar technologies. The receivers from [17] and [12] represent hybrid-integrated PICs with SiGe BiCMOS electronic ICs. In [2] a photonic SiGe BiCMOS ePIC chip is reported which achieves 28 GBd, showing QPSK data transmission.…”

A two-stage opamp frequency Compensation technique by splitting the 2nd stage

“…For this reason, Miller compensation will also be known as pole-splitting compensation. Almost every researcher has shown the math's to show the splitting but there is no intuitive explanation why poles do so [4]. Looking at the fig.…”