23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture

Rho, Kwangmyoung; Tsuchida, Kenji; Kim, Dong-Keun; Yutaka, Shirai; Jihyae, Bae; Inaba, Teruhiko; Hiromi, Noro; Hyunin, Moon; Chung, Sungkwon; Sunouchi, K.; Park, Jin-Won; Kiseon, Park; Yamamoto, Atsushi; Chung, Se-Kyo; Kim, Hyeongon; Oyamatsu, H.; Oh, Jae‐Eung

doi:10.1109/isscc.2017.7870428

Cited by 53 publications

(20 citation statements)

References 3 publications

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“…A current or a voltage signal difference between a data 295 and a reference cell is amplified by SenseAmp; maximizing this signal difference improves the SM as well as a reference cell resistance with its low variation. Researchers have sought as a way to find well-defined reference cell resistance such as only R P [8], current-mean [24,9] and resistance-300 mean [24], dynamic data dependent [18,24] and absolute resistance [27], and in this work, multiple-cell R P building serially connected R P to protect read-disturb.…”

Section: The Resistance Determination Of Reference Cellsmentioning

confidence: 99%

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Atasoyu

Altun

Özoğuz

2019

Microelectronics Journal

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In this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured with perpendicular magnetic tunnel junctions with a high tunneling magnetoresistance ratio in a low resistance-area product. To overcome the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance. We have verified that the proposed sensing scheme offers a substantial improvement in bit-error-rate performance. To enumerate the read operations of the proposed sensing scheme with the proposed cross-coupled capacitive feedback technique on the clamped circuity have successfully been performed a 2.5X reduction in average low power and a 13X increase in average reading speed compared with the previous works due to its device structure and the proposed circuit technique.

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Section: The Resistance Determination Of Reference Cellsmentioning

confidence: 99%

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Atasoyu

Altun

Özoğuz

2019

Microelectronics Journal

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“…The authors also propose partial write and write bypass optimizations in the STT-MRAM main memory that achieves performance comparable to DRAM while reducing memory energy consumption by 60%. K Rho et al [7] propose a 4Gb STT-MRAM, featuring a compact 9F2-cell that was developed using advanced technology (with the DRAM transistor). The 9090nm2 STT-MRAM was realized by using a compact gate pitch for the wordline, and an even finer metal-0 pitch for the bitline and source line.…”

Section: State Of the Artmentioning

confidence: 99%

“…The second proposal borrows from [7]. Two different supply voltages are present here to help boost the WL and compensate for the weak DRAM transistor (V dd 1 = 1.2V and V dd 2 = 1.8V).…”

Section: B Nvm Main Memorymentioning

confidence: 99%

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Perumkunnil

Rock

Hartmann

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multicore architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

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“…DRAM chip capacity gradually increased and reached 16Gb by the year 2016. Following a sharp incline, STT-MRAM chip capacity increased to 4Gb by the same year [18], reducing the capacity gap between these two technologies from 2000× in 2003 to only 4× in 2016.…”

Section: Development Trendmentioning

confidence: 99%

Enabling a reliable STT-MRAM main memory simulation

Asifuzzaman

Verdejo

Radojković

2017

Proceedings of the International Symposium on Memory Systems

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STT-MRAM is a promising new memory technology with very desirable set of properties such as non-volatility, byteaddressability and high endurance. It has the potential to become the universal memory that could be incorporated to all levels of memory hierarchy. Although STT-MRAM technology got significant attention of various major memory manufacturers, to this day, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing parameters which are required to perform a cycle accurate main memory simulation. Our study presents a detailed analysis of STT-MRAM main memory timing and propose an approach to perform a reliable system level simulation of the memory technology. We seamlessly incorporate STT-MRAM timing parameters into DRAMSim2 memory simulator and use it as a part of the simulation infrastructure of the high-performance computing (HPC) systems. Our results suggests that, STT-MRAM main memory would provide performance comparable to DRAM, while opening up various opportunities for HPC system improvements. Most importantly, our study enables researchers to conduct reliable system level research on STT-MRAM main memory, and to explore the opportunities that this technology has to offer.

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23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture

Cited by 53 publications

References 3 publications

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Enabling a reliable STT-MRAM main memory simulation

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