2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2014
DOI: 10.1109/isscc.2014.6757477
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22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

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Cited by 92 publications
(25 citation statements)
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“…The fastest electronic DAC and ADC reported to date are 92 GSa/s [46] and 90 GSa/s [47], respectively, with 8-bit resolution. High sample rates in data converters require tight control of clock jitter since aperture jitter, which is the inability of data converters to sample at precisely defined times, limits sample rate and the effective number of bits (ENOB).…”
Section: Current and Future Challengesmentioning
confidence: 99%
“…The fastest electronic DAC and ADC reported to date are 92 GSa/s [46] and 90 GSa/s [47], respectively, with 8-bit resolution. High sample rates in data converters require tight control of clock jitter since aperture jitter, which is the inability of data converters to sample at precisely defined times, limits sample rate and the effective number of bits (ENOB).…”
Section: Current and Future Challengesmentioning
confidence: 99%
“…6. High-performance DACs and ADCs have already been demonstrated in nanoscale CMOS technologies [15,17,19,21,22,23] and been put into practical use. They have high sampling rates but limited analog bandwidth of less than about 20 GHz.…”
Section: Data Converters: Dac and Adcmentioning
confidence: 99%
“…Based on the SAR ADC, an interleaved ADC architecture is presented that achieves the specifications required for the optical communication standard ITU-OTU4 [12]. The ADC achieves up to 100 GS/s at less than 1 W. First the ADC architecture is highlighted before the core component of the 649 interleaved ADC, the interleaver, is described in detail.…”
Section: Interleaved Sar Adcmentioning
confidence: 99%