20nA sub-threshold biased CMOS reference current source

Yadav, Chetali; Prasad, Sunita

doi:10.1109/icomicon.2017.8279144

Cited by 4 publications

(3 citation statements)

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“…Thus, their power consumptions are usually much higher than those implemented using "all" CMOS transistors working in subthreshold regions. [19][20][21][22][23][24] Even though subthreshold characteristics were employed, the resistors were still used to generate the current in the order of μA to 100 nA, 20,21,24) or the MOS transistor was biased at the triode region and acted as a resistor, which results in more than 200 nW of power consumption and fair temperature coefficients. 22) Some other literature 17,19,23) utilizes MOS transistors biased at the region of zero temperature coefficient to avoid the conventional resistors.…”

Section: Introductionmentioning

confidence: 99%

“…[19][20][21][22][23][24] Even though subthreshold characteristics were employed, the resistors were still used to generate the current in the order of μA to 100 nA, 20,21,24) or the MOS transistor was biased at the triode region and acted as a resistor, which results in more than 200 nW of power consumption and fair temperature coefficients. 22) Some other literature 17,19,23) utilizes MOS transistors biased at the region of zero temperature coefficient to avoid the conventional resistors. However, the MOS transistors need to be biased at strong inversion, which leads to the current close to the order of μA through the transistors.…”

Section: Introductionmentioning

confidence: 99%

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A gate leakage current based nano-ampere current reference generator using a dual threshold voltage 6-T voltage reference

Chang¹,

Tseng²,

Lin³

et al. 2022

Jpn. J. Appl. Phys.

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To realize nano-ampere current reference generator, a tunable 1.34 nA current reference generator is proposed by applying the reference voltage to a PMOSFET achieving low temperature coefficients (TCs). Unlike the conventional resistors occupying large die area, the area was significantly reduced by using the gate-leakage PMOSFET. Furthermore, the area-efficient reference voltage based on MOSFETs operated at subthreshold rather than the accurate but power- and area-hungry bandgap reference was utilized. To cope with process variations, the reference current can be trimmed by four switches and is easy to be replicated. The proposed current generator was designed and fabricated on the die area of 0.0175 mm^2 using 90 nm CMOS technology. The measured TC of the 308 mV voltage reference is 124 ppm/°C and the measured TC of the 1.34 nA current reference is 394 ppm/°C from 0°C to 120°C at a supply voltage of 0.75V.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A gate leakage current based nano-ampere current reference generator using a dual threshold voltage 6-T voltage reference

Chang¹,

Tseng²,

Lin³

et al. 2022

Jpn. J. Appl. Phys.

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“…Though, its dependency of resistances to work leads to an unsuitable option when the temperature dependence should be reduced since the final circuit is created by the addition of multiple current peaks until reaching the operational bias point [2]. The beta multiplier current reference whose resistor to bias the circuit in subthreshold operation is small, even for a value of current in nanoampere range, the drawback of this circuit is the needed of different voltages in order to bias the NMOS and PMOS transistors so the temperature and supply dependency can not be reached rapidly [4]. Other solution where the self-biased principle was used is a circuit where the temperature is compensated by gate-leakage transistors, these are biased by a reference voltage generated for a self-regulated 4T push pull circuit; in this case, occupancy area could be a problem at the design time [3].…”

Section: Introductionmentioning

confidence: 99%

Design low-voltage low-power current reference in 180nm - Diseño de un espejo de corriente a baja potencia y voltaje en 180nm

Calderon

2020

Av. Cienc. Ing. (Quito)

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This paper describes design improvement of a current reference, originally based on dual-threshold voltage current mirror stages, these stages have been modified in order to improve the temperature dependence of the current of a diode-connected transistor and the figures of merit to compare this circuit both the base-circuit. The proposed solution has been designed in a 0.18 \text{\ensuremath{\mu}m} technology and analyzed through circuit simulation. Simulation results, when a body-bias generator is used, show an output current of 342 nA and a power consumption below 513 nW at the maximum operating voltage of 1.5 V and at the room temperature. The line sensitivity is 1 %/V, while the temperature coefficient is 17 ppm/°C. On the other hand, when the body-bias generator is neglected, the circuit shows an output current of 188 nA and a power consumption below 282 nW at the maximum operating voltage of 1.5V and at the room temperature. The line sensitivity is 2.89 %/V, while the temperature coefficient is 23 ppm/°C. Resumen Hoy en día, los espejos de corriente o current reference, pueden ser mejorados con las características de inversión débil subthreshold-region cuando son construidos con tecnología CMOS, está tesis trata sobre cuatro estructuras de current reference basadas en un circuito de solo tres transistores, las figuras de merito como coeficiente de temperatura, consumo de potencia, y sensibilidad de carga y proceso son obtenidas en cada una de las estructuras, y posteriormente son comparadas para disernir cual de las implementaciones ha presentado un mejor desempeño. Las simulaciones fueron realizadas en una tecnología de 180 nm, nanómetros, TSMC CMOS usando transistores de tipo MEDIUM VOLTAGE THRESHOLD (MVT) para un voltaje máximo de alimentación de 2 y 3 voltios. La tesis esta compuesta de cuatro capítulos, el primero muestra los principios físicos para inducir una corriente cuando el transistor MOSFET se encuentra en la región de subthreshold, lineal y saturación. El segundo capitulo muestra las especificaciones tomadas en cuenta para implementar los cuatro diferentes diseños, como son el dimensionamiento y los parámetros eléctricos de las fuentes de alimentación, los diseños fueron implementados en Virtuoso de Cadence. El tercer capitulo muestra los resultados obtenidos en cada uno de los circuitos y una comparativa de las figuras de merito calculadas. Finalmente, el cuarto capitulo muestra las conclusiones de cada bloque, los beneficios obtenidos al implementar cada uno de los diseños así como la mejor solución acorde a las figuras de merito obtenidas.

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