16.2 A 76fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

Kim, Juyeop; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk

doi:10.1109/isscc.2019.8662532

Cited by 29 publications

(16 citation statements)

References 3 publications

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“…For an oscillator under the CSL regime (see Fig. 3 For a high-performance (e.g., sub-100 fs) frequency synthesizer, the reference spurs alone can substantially degrade its jitter profile, which is typically not included in the integration range of rms jitter [16], [20]. The rms jitter considering both the integrated PN (i.e., IPN dBc ) and reference spurs can be calculated as…”

Section: A Ref Spur and Rms Jitter Degradation By Frequency Offsetmentioning

confidence: 99%

“…Unfortunately, this requires a relatively complex timing control based on several digitally controlled delay lines (DCDLs). Yoo et al [17] and Kim et al [20] proposed a low-power phase-sampling-based FTL with an assumption that, in a quadrature VCO (Q-VCO), the phase of Q-VCO's Q-component could record the frequency deviation with the normal injection into its in-phase (I)-component (exploiting a natural delay for the I-component's injection affecting its Q-component). A similar idea was extended to a differential VCO in [22].…”

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confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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Section: A Ref Spur and Rms Jitter Degradation By Frequency Offsetmentioning

confidence: 99%

mentioning

confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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“…Interestingly, the GHz-reference frequency can be used as an input for the second stage of a cascaded PLL [22]. Especially in the ultra-scaled CMOS technology, it's very challenging to achieve low phase noise of the high-frequency VCO.…”

Section: F Simulated Settling Behaviormentioning

confidence: 99%

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

et al. 2020

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This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power. Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid the typical current-mode-logic (CML) circuitry for static power reduction. Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.6 mW, of which the dynamic FD and PD merely consume 0.28 mW. The integrated jitter is 415.6 fs rms (10 kHz to 100 MHz) and the reference spur level is −53 dBc at a 26.4-GHz output. INDEX TERMS CMOS, dual loop, phase-locked loop (PLL), frequency detector (FD), phase detector (PD), figure-of-merit (FoM), millimeter (mm)-wave, voltage-to-current converter (VIC), voltage-controlled oscillator (VCO), divider-by-4, dynamic latch.

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“…Recently, there has been a significant interest in employing sampling-based phase detectors (PDs) in PLL architectures due to their low noise and mostly passive implementation, thus promoting low power [9], [10]. A sub-sampling PD (SS-PD) leverages high slew-rate (K SS ) of the incoming oscillator waveform [11], which relaxes the requirements on a subsequent analog-to-digital converter (ADC) [9], [12], [13] [see Fig. 1(a)].…”

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confidence: 99%

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

Siriburanon

et al. 2021

IEEE J. Solid-State Circuits

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This article presents a low-power fractional-N alldigital phase-locked loop (ADPLL) employing a referencewaveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-todigital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0-2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoM jitter of −247 dB in a fractional-N mode. Due to the wide (largely linear) monotonic range and 4× oversampling rate from a 50-MHz reference, without any additional circuitry, the proposed ADPLL can settle within 3 µs in face of a 70-MHz frequency step.

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16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

Cited by 29 publications

References 3 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

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