15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Su, Jian‐Wei; Si, Xin; Chou, Yen-Chi; Chang, Ting-Wei; Huang, Wei-Hsing; Tu, Yung-Ning; Liu, Ruhui; Lu, Pei-Jung; Liu, Chun‐Jen; Wang, Jinghong; Zhang, Zhixiao; Jiang, Hongwu; Huang, Shanshi; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Sheu, Shyh-Shyuan; Li, Sih-Han; Lee, Heng-Yuan; Chang, Shih-Chieh; Yu, Shimeng; Chang, Meng‐Fan

doi:10.1109/isscc19947.2020.9062949

Cited by 132 publications

(31 citation statements)

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“…With respect to the circuit-level implementation of storage blocks, memory subsystems can perform the storage function as well as the associated arithmetic and computing units. IMC and NMC were investigated, and the majority of them underwent silicon verification in SRAM [4,[18][19][20][21][22] and several NVMs, including RRAM [23][24][25], STT-MRAM [26][27][28][29][30][31], spin-orbit torque (SOT), and MRAM [32][33][34].…”

Section: Circuit-level Implementationmentioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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Section: Circuit-level Implementationmentioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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“…Table I compares the performance of this chip with similar MACs fabricated in similar process nodes. We primarily focus on the comparison using the precision-scaled MAC energy, which is a figure-of-merit for MAC computation used in the latest paper [18]. Table I shows that our measured energy efficiency is about 30% better than that of the full digital MACs in the same process node and comparable to those of the mixed-signal MACs with similar resolutions that are fabricated in the same process nodes.…”

Section: Measurements and Verificationsmentioning

confidence: 99%

An 8-bit Ring-Amplifier Based Mixed-Signal MAC Circuit With Full Digital Interface and Variable Accumulation Length

Kim

Seo

et al. 2021

IEEE Access

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An 8-bit switched-capacitor multiply-and-accumulator (MAC) in 65nm CMOS is presented. Based on a cascaded low-power ring-amplifier-based switched-capacitor DACs, the MAC circuit features a programmable accumulation length in MAC computation. Fabricated in 65nm CMOS, the prototype MAC circuit achieves a precision-scaled energy efficiency of 1.32fJ per MAC operation, which is comparable to other state-of-the-art MAC circuits, along with best-in-class linearity. The noise performance has been verified using four real-world convolutional neural networks (CNNs) and 10,000-image data sets with up to 1,000 classes with an accuracy drop of less than 2% compared to the baseline 32-bit floating-point MAC.

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“…Moreover, on-chip training is also possible with SRAM based CIM architectures [19]. Most of today's SRAM CIM prototypes [20][21][22] targeted at demonstrating inference or on-chip training functionality or improving performance, while the security challenges in the SRAM-CIM designs are largely unexplored.…”

Section: Sram-based Cimmentioning

confidence: 99%