Selective Deposition of Copper with Iodine Assisted Growth of MOCVD on an MPTMS Monolayer Surface at a Low Temperature

Rahman, Mohammad Arifur; Park, Hyuk; Kim, Ara; Lee, Chiyoung; Lee, Jaegab

doi:10.3365/eml.2010.12.209

Cited by 6 publications

(3 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Deposition conditions at this time were SiH 4 0.025 slm, H 2 6 slm, and WF 6 0.28 slm [34,39,40]. The temperature was 395 • C, and the SiH 4 reduction time of the W seed formation step was 12 s [41,42]. The step coverage and filling of the thin films of CVD TiN, IMP TiN, and CVD W were analyzed using SEM and TEM, and the etching profiles were analyzed using SEM after sample treatment using precision etching coating system (PECS; Gatan, Pleasanton, CA, USA) equipment.…”

Section: Methodsmentioning

confidence: 99%

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

et al. 2019

View full text Add to dashboard Cite

This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH4 reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.

show abstract

Section: Methodsmentioning

confidence: 99%

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

et al. 2019

View full text Add to dashboard Cite

show abstract

“…Flexible Copper Clad Laminates (FCCLs) consist of metal electrodes on insulating polyimide substrates. Polyimide substrates have several excellent properties, such as high thermal stability and high chemical resistance, and they are widely used in flexible printed circuit board applications [1][2][3][4][5][6][7][8][9][10][11]. While copper is the best conductor material in electronic systems, copper electrodes on polyimide systems suffer from poor interfacial adhesion.…”

Section: Introductionmentioning

confidence: 99%

Effect of annealing on the interfacial adhesion energy between electroless-plated Ni and polyimide

et al. 2011

View full text Add to dashboard Cite

The effect of annealing on the interfacial adhesion energy between electroless-plated Ni films and polyimide substrates was evaluated using a 180-degree peel test. The measured peel strength values decrease from 263.6 ± 7.8 J/m 2 to 109.3 ± 6.4 J/m 2 after annealing for 100 h at 200°C in an ambient environment. XPS analysis on the peeled surfaces reveals that the peeling is due to cohesive failure inside the polyimide, which is related to the fact that wet treatment produces an activated bonding mechanism between electroless-plated Ni and polyimide. This implies a degradation of the polyimide structure due to oxygen diffusion through the interface between Ni and alkali wet-treated polyimide, which is also closely related to the decrease in the interfacial adhesion energy due to thermal treatment in ambient conditions.

show abstract

“…In particular, the global metallization process has been used to replace Al with Cu owing to its lower resistivity and higher electromigration resistance. [1][2][3][4][5][6][7][8][9][10] However, Cu metallization requires a diffusion barrier layer (DBL) since Cu diffuses easily into Si, SiO 2 , and other dielectric materials. In terms of contact resistance, a thinner DBL is more favorable for the performance of semiconductor devices because it has a much higher resistance than Cu.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Tungsten Nitride Deposition Using Tungsten Hexafluoride Precursor for Via and Plug Metallization

Hwang

Cho

Kim

2013

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We investigated a tungsten nitride (WN)-based diffusion barrier layer (DBL) on a Cu metal layer by atomic layer deposition (ALD) using three different treatments, namely, ammonia (NH3) plasma treatment, ammonia (NH3) pulsed plasma treatment, and diborane (B2H6) pulsed gas injection treatment. In an experimental result of a method with B2H6 pulsed gas injection, the fluorine (F) concentration was below 3% in the WN films, and optimum growth conditions, including a linear deposition rate, a few incubation cycles, good thermal stability, and an excellent step coverage of approximately 100%, were observed for the DBL application. These results suggest that the B2H6 pulsed gas injection is a useful method for obtaining high-quality WN films for use as a DBL on a Cu contact via a 15 nm node.

show abstract

Selective Deposition of Copper with Iodine Assisted Growth of MOCVD on an MPTMS Monolayer Surface at a Low Temperature

Cited by 6 publications

References 15 publications

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

Effect of annealing on the interfacial adhesion energy between electroless-plated Ni and polyimide

Investigation of Tungsten Nitride Deposition Using Tungsten Hexafluoride Precursor for Via and Plug Metallization

Contact Info

Product

Resources

About