Switching Theory

Routers are ubiquitous in modern computing, appearing in wide-area networks, multiprocessor servers, and data storage systems. Modern routers achieve high performance by solving computationally intensive tasks using custom hardware. One of the most challenging problems in designing a high-end router is scheduling the transfer of packets from inputs to outputs.We present a simple and near optimal randomized parallel scheduling algorithm for scheduling packets in routers based on the Switch-Memory-Switch (SMS) architecture, which emulates 'output queuing' by using a collection of small memories within the switch to buffer packets, and which forms the basis of the fastest routers in use today. Specifically, for a router with inputs and outputs, our algorithm computes the schedule inrounds, where a round is a communication of a few bits between input ports and memory together with simple local computation at the inputs and memory. Furthermore, by using andeep pipeline at each input, our algorithm computes the schedule in a constant number of rounds. Our pipelined algorithm is quite simple and achieves optimal (i.e., constant) throughput with a tiny ¡ £ ¢ ¤ § ¦ © delay. We show that the total amount of buffer memory required by our algorithm is close to the minimum required. We also show that the number of buffer memories is within an is the minimum number of memories needed under adversarial placement of packets. Furthermore we show that the number of extra memories that we use over the minimum of that is required in the offline version, is within a constant factor of the minimum required by any on-line scheduler, even if that scheduler is allowed to fail occasionally.Our scheduling algorithm is randomized and works with high probability in . We also prove that it has the 'self-stabilizing' property, i.e., it resumes its normal behavior if occasional lapses occur due to the probabilistic nature of the algorithm.

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“…Output queuing is strongly preferred for a number of reasons [23]. For example, it minimizes the average queuing delay faced by packets.…”

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confidence: 99%

A near optimal scheduler for switch-memory-switch routers

Aziz

Prakash

Ramachandran

2003

Proceedings of the Fifteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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“…First, switching in the quantum domain is strict-sense non-blocking. A switch is called strict-sense non-blocking if the network can always connect each idle inlet to an arbitrary idle outlet independent of the current network permutation [10]. Note that switching in the space domain is not always non-blocking.…”

Section: Advantages Of Quantum Switchingmentioning

confidence: 99%

“…First we define the connection digraph which can be used to describe the behavior of a switch at a given time, then we show how a connection digraph can be implemented using elementary quantum gates. The proposed mechanism supports unicasting as well as multicasting and is strict-sense nonblocking [10]. It can be applied to perform either circuit switching or packet switching.…”

Section: Introductionmentioning

confidence: 99%

Digital switching in the quantum domain

Tsai

Kuo

2002

IEEE Trans. Nanotechnology

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In this paper, we present an architecture and implementation algorithm such that digital data can be switched in the quantum domain. First we define the connection digraph which can be used to describe the behavior of a switch at a given time, then we show how a connection digraph can be implemented using elementary quantum gates. The proposed mechanism supports unicasting as well as multicasting, and is strict-sense non-blocking. It can be applied to perform either circuit switching or packet switching. Compared with a traditional space or time domain switch, the proposed switching mechanism is more scalable. Assuming an n × n quantum switch, the space consumption grows linearly, i.e. O(n), while the time complexity is O(1) for unicasting, and O(log 2 n) for multicasting. Based on these advantages, a high throughput switching device can be built simply by increasing the number of I/O ports.

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“…Optical interconnection networks (OINs) are able to meet many of these system requirements by leveraging the large bandwidth afforded by fiber-optic and photonic technologies [2]- [4]. Multiple-stage (or multistage) interconnection networks (MINs) offer topological advantages such as scalability and modularity owing to their composition from hundreds or thousands of similar switching node building blocks [1], [5], as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…Previous work has analyzed various performance metrics and optimization techniques for MINs [1], [5], [13]- [16] but few of these results are specific to the particulars of photonic implementation. In this work, we address the salient issues of OIN designs that specifically incorporate photonic switching element cost and complexity.…”

Section: Introductionmentioning

confidence: 99%

Optimization of multiple-stage optical interconnection networks

Small

Bergman

2006

IEEE Photon. Technol. Lett.

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Abstract-An analysis of the cost and complexity of multiplestage optical interconnection networks is presented. Because of the high cost of photonic switching elements from which these networks are composed, the radix (degree of the switching nodes) of a simple banyan network is important in determining total network cost. For most switching node cost models, it is shown that 3 3 switching nodes can actually be more efficient than 2 2 ones.Index Terms-Banyan networks, multistage interconnection networks (MINs), photonic switching systems.

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Switching Theory

Cited by 20 publications

References 0 publications

A near optimal scheduler for switch-memory-switch routers

A near optimal scheduler for switch-memory-switch routers

Digital switching in the quantum domain

Optimization of multiple-stage optical interconnection networks

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