This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semiautomatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the eventdriven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.
A low complexity low power transmitter architecture for narrow band applications is presented, consisting of two single polar transmitters for the 900 MHz and the 2.4 GHz band, respectively. Only a single 1.8 GHz local oscillator signal is used employing self-upmixing for the 2.4 GHz output. The transmitter supports arbitrary IQ modulation schemes and OFDM to fulfill the Bluetooth 4.0 "Smart", IEEE 802.15.4/Zigbee, IEEE 802.15.4g "SUN" (Smart Metering Utility Networks), and IEEE 802.11ah Sub-GHz WLAN standards. Special emphasis is placed on keeping the digital signal processing power efficient while preserving enough flexibility to fulfill all mentioned standards. The low complexity polar transmitter frontends are also described in detail. The intended output power is 24 dBm for the lower band and 13 dBm for the upper band to achieve high ranges even without additional external power amplifiers. The transmitter is used in a system-on-a-chip RF transceiver for smart utility networks and the internet of things. It has been fabricated in a 130-nm CMOS technology.
Multistandard SoC's including advanced RF and analog circuitry with digital blocks are pervasive in modern IC's. However, the system design and verification methodologies that capture the complexity of multistandard RF SoC's are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoC's, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.
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