Laterally actuated polycrystalline silicon nanoelectromechanical (NEM) relays with enhanced electrical properties are presented. Due to surface oxidation of polysilicon in room ambient conditions, the relays have a high contact resistance (> 1 GΩ) that requires high drain bias (3-5 V) to break through. The addition of a platinum sidewall coating reduces the on-resistance and the required drain bias to as low as 3 kΩ and 0.1 V, respectively. The platinum coating's stability is demonstrated by two tests: first, a contact-and-hold test where the relay passes current (~1μA) for up to 155 min and, second, a hot cycling test where the relay survives for over 108cycles . The NEMS relays are simulated using finite-element analysis, and the models are verified against experimental tests. Furthermore, the relays are configured and tested as a 2 : 1 multiplexer to show their potential as a digital logic component.

This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.Index Terms-Binary decision diagram, logic synthesis, nanoelectromechanical (NEM) relays, nanotechnology.

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