The inclusion of circuit-level blocks, such especially important for analog and RF designs because, as ring oscillators, operational amplifiers and A/D or unlike digital design where a small number of device, D/A converters, in technology characterization testchips interconnect delay and leakage metrics are sufficient to is now a well-established practice. Such Figure-of-Merit evaluate product performance, a large number of (FoM) circuit blocks provide a means of judging technology parameters affect analog and RF product technology performance and variability on-wafer performance, and the mapping from technology during the technology development phase. In addition, characteristics to product performance is complex.FoM blocks are used to validate the ability of a PDK in capturing process behavior. This paper describes an This paper describes an extension and implementation extension of this concept to the RF domain, for a high-performance 0.18,tm SiGe:C-BiCMOS of the FoM circuit block concept to RF design by technology. The design of six different RF-FoM blocks, describing the design and statistical measurement of typically found in a transceiver, is presented. Test RF-FoM blocks for a high-performance 0.18ptm structure design considerations, including layout, SiGe:C-BiCMOS technology [6]. The use of RF-FoM pad-frame choice and probe-card design, are described. blocks for the validation of a statistical PDK helped Finally, measured statistical results are presented. reduce design iterations by enabling first-pass functional These designs enabled PDK verification and engineering samples for wireless products. high-volume yield product samples.
II. TEST STRUCTURE DESIGN I. INTRODUCTIONTo be suitable as FoMs, a set of circuit blocks should The inclusion of dedicated circuit blocks in a characterization testchip is a well-established practice in satisfy a number of criteria. The circuits and logic technology development efforts [1]. A review of performances selected for inclusion in a set of FoMs the ltarot sbcsw mmust provide information about all of the key product the literature on the subject shows many different rqieet.Mroe,tog h efrac designs dedicated to standard cell characterization, and achieved tse circuts otgb the bespossible used to etemine key logc fiureof-eri achieved by these circuits may not be the best possible used to determine key logic figure-of-merit for the technology, for a FoM circuit block to be suitable performances, such as propagation delay per stage, satcnlg oio t efrac hudb ls current leakage and statistical timing [2,3]. This design to theoxece performanerof tyicl optimize to the expected performance of typical optimized family is sometimes termed Figure-of-Merit (FoM) l lv famiy i somtims tenedFigue-o-Mert (OM) designs. However, most FoM blocks are designed while designs, and recent efforts have extended the concept to design owvrmos oMbocks are dined whilê~~~~~~e dtoso h technology optimization iS ongoing, and final device the analog and RF domains [4]. Recent models are not available...
