A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered. tunable tree networks. with the final trees all driling a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50.000 resistors.capacitors. and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.
This paper describes the overall test methodology used in implementing the S/390@' microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBM's high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached. Wopyright 1997 by International Business Machmes Corporation. Copying In printed form for prwate use IS permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Juurnol reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copled or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.
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