As transistor dimension becomes smaller and with the switch to high-k metal gate (HKMG) integration, the need for a sidewall protection layer that is conformal yet meets the low thermal budget requirement becomes critical. In this work, we evaluated PEALD SiN as spacer material in comparison to PECVD SiN, at two different stresses (compressive and tensile) and two different deposition temperatures. Material characterization reveals that PEALD SiN has lower hydrogen impurities, higher density and better resistance against wet chemistry, indicating superior material quality. In addition, film conformality and pattern density characteristics for all PEALD SiN films are significantly improved over PECVD SiN. These improvements in film characteristics help drive improvement in electrical properties for devices with PEALD SiN spacer.As transistor scaling continues and with the implementation of high-k metal gate (HKMG) in Complementary Metal-Oxide Semiconductor (CMOS), there is a critical need for a highly conformal sidewall protection layer. To prevent oxidation of the high-k layer and out diffusion of implants, the sidewall protection layer must be deposited at a relatively low deposition temperature. Furthermore, as transistor designs increase in complexity, this encapsulation layer or spacer must be conformal and not sensitive to wafer loading conditions. Traditionally, the spacer is deposited using chemical vapor deposition (CVD). 1,2 LPCVD SiN is known for having good conformality but its deposition occurs at high temperature (>700 • C). As the need arises for a spacer with a lower thermal budget, plasma enhanced CVD (PECVD) SiN has been used. With PECVD SiN, deposition temperature can be lowered to ∼400 • C. However, PECVD SiN has worse conformality compared to LPCVD SiN. Moreover, CVD processes are gas-phase reaction limited and thus the film growth is sensitive to loading conditions. As chip designs become more complex, with each chip having regions with different transistor densities, it is critical to have a spacer process that is not pattern density dependent.Atomic Layer Deposition (ALD) is a deposition technique which has a clear advantage of lower deposition temperature and excellent conformality. 3,4 The development of ALD SiN processes for various applications has been reported in the literature. Hong et al. reported ALD SiN layer and SiN/SiO 2 /SiN multi layers as a gate dielectric for flash memory. 6 For spacer application in 90 nm technology, it has been reported that using ALD SiO 2 and ALD SiN as spacer and silicide blocking layer resulted in improved short channel effects. The ALD SiN was deposited at 595 • C using dichlorosilane and NH 3 . 6 The main disadvantage of ALD compared to PECVD and LPCVD is its higher cost of ownership. This, however, is beyond the scope of this work.Plasma enhanced ALD (PEALD) has been gaining popularity and recently more new PEALD processes are being developed. 4,7-10 A comprehensive review article covering the basics of PEALD, its advantages and challenges had been ...

ZrO2 is of very high interest for various applications in semiconductor industry especially as high-k dielectric in metal–insulator–metal (MIM) capacitor devices. Further improvement of deposition processes, of material properties, and of integration schemes is essential in order to meet the strict requirements of future devices. In this paper, the authors describe a solution to solve one of the key challenges by reducing the process time of the bottle neck high-k atomic layer deposition (ALD). The authors extensively optimized the most common ALD process used for the ZrO2 deposition (TEMAZ/O3) resulting now in a doubled growth rate compared to the published growth rates of maximum 1 Å/cycle. Chemical reactions explaining the origin of the high growth rate are proposed by theoretical process modelling. At the same time, the outstanding electrical properties of ZrO2 thin films could be preserved. Finally, the integration of the ZrO2 process in MIM capacitor devices with TiN electrodes was evaluated. Thereby, the known effect of TiN bottom electrode oxidation by the O3 process was analyzed and significantly reduced by different integration approaches including wet chemical treatments and ALD process variations. The resulting MIM capacitors show low leakage current and high polarity symmetry.

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A physical vapor deposition tool for 300 mm wafers was coupled with an angle resolved photoelectron spectroscopy tool (ARXPS) and used to study the growth of TaN single layer and TaN/Ta double layer diffusion barriers. The nitrogen content of TaN was adjusted by controlling the nitrogen flow and by varying the deposition power. We describe a process recipe that allows us to decrease the TaN thickness while still maintaining the Ta layer in the low resistivity -phase. The process recipe was developed on blanket wafers and evaluated in a test structure for high performance CMOS products

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