Assembly evaluations showed that the choice of the assembly process was strongly dependent on the die size, interposer design and interposer process. Choice of flux also affected the ubump assembly yield and underfill flow. Underfilling experiments confirmed that optimization of underfill process required optimization of dispense pattern, ubump parameters. Reliability evaluations showed that the reliability was affected by choice of underfill, interposer cleaning, and die thickness/package structure. One of the common failure modes was delamination between interposer and C4 underfill.
In this paper we use the constitutive equation of Bhave et al. (1993) for rod-like, liquid-crystalline polymer solutions to analyze the isothermal, steady-state spinning of these liquids in order to understand the evolution of microstructure, predict the velocity and normal stress distributions in the filament, and examine the effect of different upstream microstructural conditions. Our analysis shows that in contrast to fiber spinning models of isotropic liquids, the velocity, structure, and stress profiles are sensitive to the choice of initial conditions. In addition we have investigated the impact of the closure approximation used in the constitutive equation of Bhave et al. on the fiber spinning problem by solving the equation for the distribution function directly; only slight changes are seen in the velocity and stress profiles. An apparent elongational viscosity defined as the ratio of normal stress difference to strain rate at the takeup compares very well with the true elongational viscosity η̄ for the model, thereby suggesting that fiber spinning flows can be used to determine η̄ for liquid-crystalline polymer solutions. Model predictions of the velocity and stress agree well with data obtained by Prilutski (1984) for HPC/acetic acid solutions. Finally, we present a linear stability analysis of the spinning problem to show the impact of viscoelasticity, inertia, gravity, and surface tension on the onset of draw resonance instabilities. The neutral stability curves obtained for dominant viscoelastic forces reflect trends in the apparent elongational viscosity. Model predictions are in qualitative agreement with the draw resonance data reported by Prilutski.
Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention.Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents the reliability results as well as micro-bump resistance data. In addition, pre-conditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.Furthermore, this paper details the outstanding TSV KeepOut-Zone study (KOZ) for an active silicon interposer and the effect of TSV stress on transistor electron and hole mobility. Finally, an advanced thermal study of TSV interposer technology is presented to cool down a high-performance 28nm logic die (thousands of micro-bumps) that is mounted on a large silicon interposer with Cu through silicon via. Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. IntroductionAs the interconnect density is continuing to shrink, and the cost of fabricating finer pitch substrate is increasing, flip chip packaging with the conventional organic buildup substrate is facing a major challenge in fine pitch wiring. To address these needs, TSV interposer has emerged as a good solution [1][2][3]. TSV interposer provides high wiring density interconnection, minimizes CTE mismatch between the Cu/low-k die and the copper filled TSV interposer, and improves electrical performance due to shorter interconnection from the chip to the substrate.TSV interposer wafers are manufactured by etching vias through silicon wafers and filling the vias with metal. The two TSV methods commonly used in industry involve "viafirst/via-middle" and "via-last" process flows. The work in this paper uses the "via-first/via-middle" flow since it offers the greatest benefit of interconnect density.Typically, the TSV vias are etched using DRIE process to form a high aspect ratio via. The TSVs are typically 10-20 um in diameter and 50-100 um deep. The walls of the TSV are lined with SiO2 dielectric. Then, a diffusion barrier and a copper seed layer are formed. The via hole is filled with
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