This paper introduces a real-time on-chip power and temperature sensor for active power management in scaled CMOS technologies. In a distinct departure from earlier power estimation techniques, this sensor measures the voltage drop due to a current load and converts it into pulse counts to get a power estimate in real time. Linear regression is used to estimate load current based on the measured output frequency at a given temperature. The same sensor is also used to estimate temperature in a mode where output time period decreases linearly with temperature. Measurement results show accuracy to within for temperature estimation in the range of 22 -100 and within 10% of the actual power consumed (for loads 3.3 mA). Fabricated in 45-nm SOI technology, this power and temperature sensor occupies an area of and has a power overhead of 120 at 1.2 V supply.Index Terms-Low power, on-chip sensor, power management, power sensor, temperature sensor.
CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for a new design methodology that can provide high yield and reliability under severe parametric variations. Although several post-silicon calibration and repair strategies have been proposed to address the PVT variations, no coherent design strategy for a SoC has been developed so far. We espouse a self-healing technique based on real-time sensing and built-in feedback due to its inherent advantage of dynamic adaptation to temporal variations. This tutorial paper outlines our vision of improving marginalities in deep scaled CMOS technologies using a generic and systematic self-healing design including a system-level auto-correction algorithm. It also illustrates this methodology with design examples.
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