This paper introduced a scheme of BPSK (Binary Phase Shift Keying) carrier synchronization based on all digital Costas loop. The principle and implementation of every module used in Costas loop were demonstrated in detail and some of them were optimized to shorten the carrier recovering time. The functional simulation with the ModelSim shows the digital Costas loop works well and its carrier synchronization could be reached in only several cycles. The proposed Costas loop are implemented in FPGA chip and verified by Altera built-in SignalTap logic analyzer. For the implementation with Altera Cyclone IV EP4CE115F29C7N chip, the entire digital Costas loop only occupies a very small part of FPGA resources.
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