A novel pixel circuit for active-matrix OLED has been developed and simulated. The circuitry is voltage-driven which compensates not only the threshold voltage (V th ) for TFT device but also the power voltage (PV dd ) for OLED. In this scheme, only one capacitor (C st ) is required to store the V th of the driving TFT as well as to hold the data during one frame time. The voltage drop of PV dd due to large current flown on the power line can also be cancelled out, which improves the uniformity of the brightness. The circuit operation and simulation results will be described and presented.

In this paper, significant progresses on low‐temperature poly‐Si (LTPS) backplane technologies as well as active‐matrix organic light emitting diode (AMOLED) architectures were demonstrated and reported. In order to make display more compact, reliable and further reduction in the cost, system‐on‐panel (SOP) was realized with good device performance and small design rule capability. Moreover, over the past few years, many hypes on AMOLED have been announced, but less achievement was done for production activity. To overcome these technical challenges such as non‐uniformity, power consumption and higher resolution issues, several approaches are proposed for AMOLED displays

The characteristics of ITO film on different under‐layers including Si‐containing insulators and organic materials were investigated. It was found that the visible light transmittance of ITO film on different under‐layer is maintained, however, the surface morphology of ITO film depends strongly on different underlayers. The surface roughness of ITO film on the organic materials is 3 times larger than that on insulating materials. Also observed is the strong dependent of surface roughness on luminance efficiency. Base on these results, a new pixel structure is proposed for AM‐OLED applications. With this new pixel structure, the good properties of ITO film can be obtained and used for high efficiency and long lifetime AM‐OLED displays.

A fully self‐aligned low‐temperature poly‐silicon (LTPS) TFT process with symmetric LDD structure is developed. The gate insulator is deposited, then the insulator is etched during gate etching step with well‐controlled LDD structure. With this insulator foot, the source/drain of NMOS or PMOS is self‐aligned doped and the length of insulator foot controls the leakage current. In this paper, we discussed the effect of insulator foot in NMOS and PMOS, and we found the TFT characteristics of NMOS and PMOS are good enough for both pixel and driver applications.

A new low‐temperature polycrystalline‐silicon LTPS process was developed. The doping mask for p‐type TFT was compared with PR mask and gate hard mask. The process and design challenge in gate hard mask was compared with the photo resist residues problem encountered in PR mask process. In the gate hard mask technology, the gates of p‐type and n‐type TFTs are etched in different steps for p‐type TFT S/D doping and n‐type TFT LDD doping. The results indicate the gate insulator loss and the CD loss due to these different etching steps can be controlled in the same magnitude, and the TFT electrical characteristics of NMOS and PMOS are good enough for pixel and driver applications.