In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16×16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.
I. INTRODUCTIONH.264/AVC is the most recent and promising international video standard to provide improved coding efficiency and network adaptation. Therefore, H.264/AVC provides superior performance compared with previous standards such as and H.263 at the expenses of a prohibitive computational cost for real time applications. In particular, motion estimation is the most intensive task in the whole encoding system because of the variable block-size motion estimation (VBSME) algorithm and the multiple reference frames technique. According to the profiling of the H.264 encoder as shown in Fig.1, the computational complexity of the integer motion estimation (IME) consumes close 60% of the whole encoder. For this reason, efficient algorithm and corresponding hardware architecture for IME are essential to meet realtime video coding.
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