This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to 230 times that of software with an average 63 times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

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Abstract

This paper describes the Passive Active RFID Tag (PART). The first innovation is an automated method to generate RFID tag controllers based on high-level descriptions of a customised set of RFID primitives. We are capable of targeting microprocessor-based or custom hardware-based controllers. The second innovation is a passive burst switch front-end to the active tag. This switch reduces power consumption by allowing the active transceiver and controller to sleep when no reader is querying the tag. When RF energy is supplied by the reader, the burst switch 'wakes-up' the tag to process the primitive. A prototype burst switch is demonstrated using a Real-Time Spectrum Analyser (RTSA) from our RFID Center for Excellence. We demonstrate the customised RFID tag controller with 40 primitives using a Xilinx Coolrunner-II requiring 1.29 mW and 50 µW of power when active and asleep, respectively. We also present a PIC-microcontroller and hardwarebased Nano Tag at 2.7µW.

The architecture of modern FPGAs contain over one thousand small memory banks, over five hundred 4k-bit memory banks, and over one hundred thousand logic elements. This inherent parallelism of an FPGA makes it an ideal platform for a multiprocessor architecture. In addition to embedded memory, numerous ASIC multipliers are embedded into the FPGA architecture. This paper introduces a Single-Instruction-Multiple-Data (SIMD) system comprised of 2,4, 8, 16, 32, 64 and 88 processing elements that are built around the ASIC multipliers and controlled by a central instruction stream. In addition to the function of the ASIC multiplier, we have augmented each PE with "custom instructions" to show how the instruction set can be extended. The 88 processors SIMD design utilizes 100% of the DSP blocks available in the Altera Stratix EPS80F1508C6 device, but only 17% of the look-up table logic, which leaves 83% of the logic cells available for custom instructions.

While RFID is starting to become a ubiquitious technology, the variation between different RFID systems still remains high. This paper presents several prototyping environments for different components of radio frequency identification (RFID) tags to demonstrate how many of these components can be standardized for many different purposes. We include two active tag prototypes, one based on a microprocessor and the second based on custom hardware. To program these devices we present a design automation flow that allows RFID transactions to be described in terms of primitives with behavior written in ANSI C code. To save power with active RFID devices we describe a passive transceiver switch called the "burst switch" and demonstrate how this can be used in a system with a microprocessor or custom hardware controller. Finally, we present a full RFID system prototyping environment based on real-time spectrum analysis technology currently deployed at the University of Pittsburgh RFID Center of Excellence. Using our prototyping techniques we show how transactions from multiple standards can be combined and targeted to several microprocessors include the Microchip PIC, Intel StrongARM and XScale, and AD Chips EISC as well as several hardware targets including the Altera Apex, Actel Fusion, Xilinx Coolrunner II, Spartan 3 and Virtex 2, and cell-based ASICs.

This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior of each primitive is specified using ANSI-C within the template to automatically generate the tag controller. Two power saving components, a passive transceiver/burst switch and a smart buffer, are presented to save power and increase tag lifetime. Based on a test program, the processors required 183, 43, and 19 µJ per transaction for StrongARM, XScale, and EISC processors, respectively. Three hardware controllers using a Fusion FPGA, Coolrunner II CPLD, and ASIC required 13 nJ, 1.3 nJ, and 0.07 nJ per transaction.

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