This paper presents a predictive model for the Negative Bias Temperature Instability (NBTI) of PMOS under both short term and long term operation. Based on the reactiondiffusion (R-D) mechanism, this model accurately captures the dependence of NBTI on the oxide thickness (tox), the diffusing species (H or H2) and other key transistor and design parameters. In addition, we derive a closed form expression for the threshold voltage change (∆V th ) under multiple cycle dynamic operation. Model accuracy and efficiency were verified with 90nm experimental and simulation data. We further investigated the impact of NBTI on representative digital circuits.
Positive acceleration in the head to toe direction (+Gz) causes a reduction in blood circulation to the head which adversely affects the central nervous system and causes a decrease in vision. It has been established that Positive Pressure Breathing enhances +Gz tolerance by increasing head level blood prerssure.Utilizing the NAWC centrifuge, eight subjects outfitted with Navy Combat Edge (NCE) protective systems were exposed to a series of +Gz Rapid onset Rate (ROR) profiles and Positive Pressure Breathing schedules. Stroke Volume (SV), Heart Rate (HR), and Cardiac Output (CO) were measured using a new Impedance Cardiograph (ICG), the Drexel patented IQ system. Blood Pressure (BP), local blood volume using an Infrared Plethysmograph (IRP), Respiratory rate, and Peripheral light loss were also measured. These parameters were used to investigate potential alternate Positive Pressure Breathing Schedules to enhance the tactical pilots' +Gz tolerance.
In this paper 1 we propose a framework for Statistical Static Timing Analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations.
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