Considering the development of faster power electronic switches, especially silicon carbide (SiC) devices, parasitic elements, such as stray inductances and capacitances, become more and more crucial. Overvoltages caused by stray inductances in combination with fast switching transients can destroy the devices at turn-off. In this paper the implementation of the DVRC circuit for silicon carbide bipolar junction transistors (BJTs) is investigated. The DUT was Fairchild`s FSICBH057A120 (VCES = 1200 V, Ron = 57 mΩ).
Bipolar silicon carbide devices are attractive for high power applications offering high voltage devices with low on-state voltages due to plasma flooding. Unfortunately, these devices suffer from bipolar degradation, which causes a significant degradation of the on-state voltage. To explore the generation of stacking faults, which cause the degradation, the impact of the current density and temperature on bipolar degradation is investigated in this work. The analysis is done by stressing the base-collector diode of 1.2 kV bipolar junction transistors (BJTs) as well as the BJTs in common-emitter mode operation with different current densities at different temperatures.
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