With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. The framework is used to develop the Lightness Indicator System (LIS ) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. The LIS targets state-of-the-art multi-core processors and highend Field Programmable Gate Arrays (FPGAs). The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation.
The problem of finding the solution of partial differential equations (PDEs) plays a central role in modeling real world problems. Over the past years, Multigrid solvers have showed their robustness over other techniques, due to its high convergence rate which is independent of the problem size. For this reason, many attempts for exploiting the inherent parallelism of Multigrid have been made to achieve the desired efficiency and scalability of the method. Yet, most efforts fail in this respect due to many factors (time, resources) governed by software implementations. In this paper, we present a hardware implementation of the V-cycle Multigrid method for finding the solution of a 2D-Poisson equation. We use Handel-C to implement our hardware design, which we map onto available field programmable gate arrays (FPGAs). We analyze the implementation performance using the FPGA vendor's tools. We demonstrate the robustness of Multigrid over other similar iterative solvers, such as Jacobi and successive over relaxation (SOR), in both hardware and software. We compare our findings with a C + + version of each algorithm. The obtained results show better performance when compared to existing software versions.
The Internet-of-Things (IoT) is a revolutionary technology that is rapidly changing the world. IoT systems strive to provide automated solutions for almost every life aspect; traditional devices are becoming connected, ubiquitous, pervasive, wireless, context-aware, smart, controlled through mobile solutions, to name but a few. IoT devices can now be found in our apartments, places of work, cars, buildings, and in almost every aspect of life. In this investigation, we propose an IoT system Development Model (IDM). The proposed IDM enables the development of IoT systems from concept to prototyping. The model comprises concept refinement pyramids, decision trees, realistic constraint lists, architecture and organization diagrams, communication interface patterns, use cases, and menus of analysis metrics and evaluation indicators. The investigation confirms that the proposed model enjoys several properties, such as, clarity, conciseness, thoroughness, productivity, etc. The model is deployed for a variety of systems that belong to heterogeneous areas of application; the model is proven to be effective in application and successful in integrating mobile solutions. This chapter includes the presentation of the IDM sub-models, the reasoning about their usefulness, and the technical developments of several systems. The chapter includes thorough discussions, analysis of the model usability and application, and in-depth evaluations. 23 rely on services hosted by a third-party Internet provider. Here, the interfacing device and the user fully communicate through the third-party provider, such as, a webserver, database server, application server, etc. RECON adopts the second CI model that comprise a server-based interface with a dedicated Internet Protocol (IP) address. All the presented systems benefit from the third model that enables a direct communication between the user and the processing system when the user and the device are at the same location. Indeed, in all the presented applications, the user communicates with the system using a mobile solution that can be an application or a web-interface using a browser. Figures 14 and 15 show snapshots of the mobile user interfaces of RECON and NFC Wallet.
2Reconfigurable Hardware Implementation of the SOR Method the system at hand. There are two basic approaches for solving linear systems: Direct Methods and Iterative Methods. In the first approach, a finite number of operations are performed to find the exact solution. In the second approach, an initial approximate of the solution is generated, then this initial guess is used to generate another approximate solution, which is more accurate than the previous one [12] The robustness of applying iterative methods over direct methods is shown in different areas including: circuit analysis and design, weather forecasting and analyzing financial market trends.The well-known iterative methods are: Gauss-Seidel, Multigrid, Jacobi and Successive Over-Relaxation (SOR) which is of a interest in this chapter. SOR has been devised to accelerate the convergence of Gauss-Seidel and Jacobi [13], by introducing a new parameter, , referred to as the relaxation factor. The SOR rate of convergence is highly dependent on the relaxation factor. The main difficulty of using SOR is finding a good estimate of the relaxation factor [12]. Several techniques have been proposed for determining the exact value of which accelerates the rate of convergence of the method [12,13].All available iterative methods packages, including SOR, are done in software. Examples are the: ITPACK 3A, ITPACK 3B, ITPACK 2C, ITPACK 2D, and the ELLPACK package [14,15]. Several sequential and parallel techniques were used in these packages to accelerate the method [16].The emergence of the new computing paradigm, Reconfigurable Computing (RC), introduces novel techniques for accelerating certain classes of applications including signal processing (e.g., weather forecasting, seismic data processing, Magnetic Resonance Imaging (MRI), adaptive filters), cryptography and DNA matching [17]. RC-systems combine the flexibility offered by software and the performance offered by hardware [18]. It requires a reconfigurable hardware, such as an FPGA, and a software design environment that aids in the creation of configurations for the reconfigurable hardware [17].In [19], the first hardware implementation of an iterative method-the Multigridis presented. The speedup achieved demonstrates that hardware design can be suited for such computationally intensive applications. Toward proving the hypothesis that accelerated versions of the iterative methods can be realized in hardware, we undertook the first hardware implementation of the SOR method; using the same FPGAs that were used in [19][20][21].In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher-level design tool to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i and Quartus II 5.1). We target Virtex II Pro, Altera Stratix and Spartan3L which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them ...
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