Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12"/300 mm diameter. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 24"×18" or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As a process alternative also lamination as used e.g. in PCB manufacturing can be taken into account.=Within this paper the evaluation of panel level compression molding with a target form factor of 24”*18” / 610×457 mm2 is described. The large panel size equals a typical PCB manufacturing full format and is selected to achieve process compatibility with cost efficient PCB processes. Here not only conventional compression molding is considered but also the new process compression mold lamination is introduced as a tool-less mold alternative. Panel level molding is compared to 8” and 12” wafer molding as well as to low cost PCB 24”×18” lamination focusing on manufacturing challenges, high volume capability and estimated cost. Technological focus of this study will be the evaluation of liquid, granular and sheet molding compound. This includes thorough material analysis regarding the process relevant material properties as reactivity or viscosity. One key process step for homogeneous large area embedding is material application before compression molding. Where sheet compounds already deliver a uniform material layer the application of liquid and granular compound must - e optimized and adapted for a homogeneous distribution without flow marks, knit lines and incomplete fills. Hence, dispense patterns of liquid and granular molding compounds are studied to achieve high yield and reliable mold embedding. In addition applicable thickness ranges, total thickness variations, void risks and warpage will be investigated for the different material types. The overall a process flow will be demonstrated for selected compression mold variants resulting in a 24”×18” / 610×457 mm2 FOPLP using PCB based redistribution layer (RDL) as low cost alternative to thin film technology. For=PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using laser direct imaging (LDI) techniques for maskless patterning. All process steps are carried out on full format 24”×18” / 610×457 mm2
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18"×24" or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed
No abstract
Today’s microelectronics packaging especially for SiPs relies on the processing of a wide variety of materials. Materials for components, for substrates, for contact materials (solder & adhesives) and encapsulants. Most materials are processed as bulk material but precision dosing of pastes is key to many assembly processes. Examples are dosing of solder paste, typically done by stencil printing, Underfilling for Flip Chip encapsulation, typically done by dispensing or jetting, or Glob Top encapsulation of Chip on Board assemblies, where also dispensing is the typical process. When working with those paste materials, viscosity is one of the key parameters for processing, and viscosities too high do not allow dosing of the materials, not even to transport the material from a reservoir to the dosing head, which may be a simple needle or a jet valve. [i, ii] To overcome this obstacle, i.e. to dose materials of high viscosity precisely and homogeneously from a syringe to the dosing head, a research program has been set up, where Vermes microdispensing as a valve manufacturer and TU Berlin/IZM as a research institute are cooperating. TU Berlin is working on material rheology effects and flow models; Vermes is researching valves modifications and material flow path optimization. Core of the research is to find methods that allow a reduction of paste viscosity without leading to irreversible changes in the material, as would be the case when simply applying heat to the paste. As reference process for material dosing, FO-WLP has been chosen, materials selected for the investigations are GlobTop dam and fill material and liquid molding compound – using both rheological experiments as well as actual material dosing and processing. Apart from temperature, mechanical and ultrasonic stimulation of the material have been evaluated to achieve optimized dosing of high viscous pastes, As a result, a first description of paste behavior during processing is given, being the basis for future work towards homogeneous precision dosing of high viscous pastes for microelectronic applications
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