The effect of the structural variation of device on its thermal resistance was investigated for trench-isolated bipolar transistors. Devices with various number of emitter segments and inter-segment spacings and several different trench-tu-emitter distances were fabricated and the thermal resistance was measuredcornpared. An analytical thermal model was also developed and provided a good prediction on the structural dependence of the thermal resistance, exhibiting a good agreement with the measurement. 2D thermal device simulation was performed to obtain detailed temperature distribution inside the devices.
An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.
This paper investigates high-current and electrostatic discharge (ESD) phenomenon in pseudomorphic epitaxial-base silicongermanium (SiGe) heterojunction bipolar transistors (HBT). Transmission line pulse (TLP) and ESD human body model (HBM) wafer-level reliability testing, failure analysis and simulation of SiGe HBT devices is completed for high-current characterization and evaluation of the ESD robustness of a BiCMOS SiGe technology.
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