A dynamic frequency divider with 82.4GHz maximum operating frequency, the fastest reported in any semiconductor technology, and a static frequency divider with 60GHz maximum operating frequency, the fastest reported in Si, are intended for future millimeter-wave systems. These frequency dividers are fabricated in self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs). These SiGe HBTs provide a 122GHz cutoff frequency, a 163GHz maximum oscillation frequency, and 5.5ps ECL gate delay, the fastest reported in Si.The growing demand for consumer radar systems (automotive radars) and wide-bandwidth radio communications (WLAN-wireless local area networks, LMDS-local multiple distribution services) systems, are met by rapid advances in development of monolithic millimeter-wave ICs (MMWICs), given the availability of large-bandwidth spectrums and the allocation of such frequency bands for commercial use. Over the last decade, they have been mainly based on III-V compound semiconductor devices. The highspeed frequency divider (FD) is a key circuit for applications which require frequency-division. Accordingly, given the demand for high speed FD ICs operation at frequencies of over 60GHz are previously reported: two types of analog dynamic FDs (ADFDs) with operating frequencies of 57-64GHz for GaAs HEMTs [1] and of 75GHz for InP HEMTs [2]; and a digital dynamic FD (DDFD) with operating at 39 to 63.5GHz for InP HEMTs [3]. However, the locking range of an ADFD is narrow given a fixed bias condition and the operating frequency of the DDFD is far below the 77GHz allocated to automotive radar systems. Furthermore, to enable use of millimeter-wave systems in consumer and commercial electronics, low-cost monolithic ICs are essential. Only Si MMWICs have a chance of overcoming these hurdles.A schematic cross-section of a 0.2µm self-aligned SEG SiGe HBT is shown in Figure 12.8.1 [4]. The 0.6µm-wide SiGe-base and Si-cap multilayer, self-aligned to the 0.2µm-wide emitter, is selectively epitaxial grown by using a UHV/CVD system. Collector capacitance and base resistance are effectively reduced using a poly-Si assisted self-aligned SEG (PASS) structure [5]. To obtain high-speed characteristics, the 15nm-thick 2x10 19 cm -3 boron-doped Si 1-x Ge x layer with a 10nm-thick dual-graded Ge-profile is applied. To reduce parasitic resistances of all electrodes, Ti-salicide layers are formed. To reduce collector and substrate parasitic capacitances, shallow-trench and deep-trench isolation (STI and DTI) structures are used. 4-level interconnects, with MIM capacitors formed between the first and second metal layers by using plasma SiO 2 as an insulator, are formed by chemical mechanical polishing. Except for the SEG of SiGe, the process used to fabricate this SiGe HBT is almost the same as the well-established 0.2µm bipolar-CMOS technology for fast-cache memory chips and can easily be extended to producing devices integrated with CMOS.Typical transistor characteristics of a SiGe HBT with an emitter area of ...
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