This paper presents a two-stage, compact, powerefficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm', it is very suitable as a VLSI library cell. The floating class-AB control is shifted into the summing circuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current source biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which provides a power-supply-independent quiescent current. Using the compact architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation has been realized. The opamps have, respectively, a bandwidth-to-supplypower ratio of 4 MHdmW and 11 MHdmW for a capacitive load of 10 pF.
Abstruct-This paper presents a two-stage, compact, powerefficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm', it is very suitable as a VLSI library cell. The floating class-AB control is shifted into the summing circuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current source biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which provides a power-supply-independent quiescent current. Using the compact architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation has been realized. The opamps have, respectively, a bandwidth-to-supplypower ratio of 4 MHdmW and 11 MHdmW for a capacitive load of 10 pF.
Abstruct-The paper presents a rail-to-rail class-AB operational amplifier in a standard Vth =0.6 V CMOS technology operating at 1.5 V. A hybrid nested Miller compensation technique yields 6 MHz unity gain frequency at 300 pA supply current, 120 dB gain and programmability. Operation down to 1.0 V at 15 //A is possible with 400 kHz UGF. The die area of the chip is 0.05 mm2 (70 mil').
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