The easiest way to improve the quality and decrease the size of the integrated passive components is to improve their layout. On-wafer CMOS inductors with different layouts of metal coils aimed at optimizing the component characteristics are processed, measured, and analyzed. Narrow extra wires at the edges of spirals and continuous via arrays in the spirals are found to be effective, when peak value of quality factor (Q) and resonance frequency (fres) are considered the critical parameters.
New packaging materials make it possible to produce flexible system in package (SIP) and system on package (SOP) modules. However, in these the integrated circuits are exposed to increased mechanical stresses. The stresses may become even more severe when thinned chips are used. The effect of mechanical stress on the characteristics of on-wafer capacitors was studied. The mechanical stress increased clearly the resonance frequency of poly-insulator-poly capacitors, but caused only minor impedance changes for metal-insulator-metal capacitors. No fatal stress-induced phenomenon was found and the on-wafer capacitors should also operate correctly in SIP and SOP modules. The test chips were processed with two different complementary metal oxide semiconductor processes and the tested on-wafer capacitors had values of 4.8–47pF.
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