Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a 28Si/28SiO2 interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.
Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.
Here, we report a novel method for low-temperature synthesis of monolayer graphene at 450 °C on a polycrystalline bimetal Ni-Au catalyst. In this study, low-temperature chemical vapor deposition synthesis of graphene was performed at 450 °C on codeposited Ni-Au which shows successful monolayer graphene formation without an extra annealing process. The experimental results suggest that electron beam codeposition of bimetal catalyst is the key procedure that enables the elimination of the pre-growth high-temperature annealing of the catalyst prior to graphene synthesis, an indispensable process, used in previous reports. The formation was further improved by plasma-assisted growth in which the inductively coupled plasma ionizes the carbon precursors that interact with codeposited Ni-Au catalyst of 50 nm in thickness at 450 °C. These combined growth conditions drastically increase the graphene’s sheet uniformity and area connectivity from 11.6% to 99%. These fabrication parameters enable the graphene formation that shifts from a bulk diffusion-based growth model towards a surface based reaction. The technique reported here opens the opportunity for the low-temperature growth of graphene for potential use in future CMOS applications.
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