The degradation behavior of integrated Pt/SrBi2Ta2O9/Pt capacitors by hydrogen impregnation during the intermetal dielectric deposition and passivation is investigated. The hydrogen ions generated as a reaction byproduct from the SiH4-based deposition processes of the dielectric films induce reduction in the remanent polarization (Pr) as well as the imprint behavior of the small size capacitors (2×2 μm2). The degree of degradation is quite dependent on the size of the individual capacitors. The smaller capacitors underwent more serious degradation implying that the hydrogen ions impregnate into the SBT layer mainly along the etched side area of the capacitors not through the top Pt electrode. Metallization adopting TiN/Al/TiN/Ti multilayer is very effective in suppressing the hydrogen impregnation. In particular, the Ti layer appears to block the hydrogen penetration. Therefore, the optimized metallization scheme, wider metal lines than the top electrode area by 1 μm, successfully protects the integrated capacitors from the hydrogen damage. 12 μC/cm2 of 2Pr and 1.1 V of 2Vc (coercive voltage) with an imprinting voltage of 0.16 V were obtained from the passivated 2×2 μm2 array capacitors by the optimized metallization.
The thermal stress effects of the inter-level dielectric (ILD) layer on the ferroelectric performance of integrated Pt/SrBi2Ta2O9(SBT)/Pt capacitors were investigated. Two different thin film materials, pure SiO2 grown at 650 °C and B- and P-doped SiO2 grown at 400 °C by chemical vapor deposition techniques, were tested as an ILD layer. The ILD layer encapsulated the SBT capacitor array. During high temperature thermal cycling (up to 800 °C) after ILD deposition, which is used for both densifying the ILD and curing of the various damage imposed on the SBT capacitors, a large thermal stress occurred in the bottom Pt layer due to the thermal expansion mismatch between the various layers. In particular, the pure SiO2 ILD layer between the capacitors did not allow thermal expansion of the Pt layers, which led to a large accumulation of compressive stress in the layer. This resulted in hillock formation in the bottom Pt layer and eventual capacitor failure. However, the B- and P-doped SiO2 ILD layer contracted during thermal cycling by removing residual impurities, which allowed greater expansion of the Pt layer. Therefore, compressive stress accumulation did not occur and excellent ferroelectric properties were thus obtained from the integrated capacitor array.
We report on a hydrogen barrier necessary for a conventional passivation process of integrated SrBi2Ta2O9 (SBT)-based memories. The passivation process significantly degraded electrical properties of the memories, resulting from hydrogen damage in the SBT capacitors. Metallic films (Ti, TiN, and Al) were investigated as a hydrogen barrier during the passivation process. The Ti(>500 Å) hydrogen barrier only showed the electrical properties of memories free from hydrogen damage. The formation of stable hydrides and the suppressed diffusion of hydrogen through the Ti films during the passivation processes resulted in sufficient switching polarization, low leakage current, and good reliabilities at high temperature.
We present a novel device architecture for low set and reset currents in phase change random access memory (PCRAM). In this structure, the sidewall of phase-change film is contacted with the vertical heating layer. In particular, to realize a small contact area of under 50 nm 2 for low reset current, this structure includes stacked layers consisting of extremely thin phase change material (PCM) and conduction films, the fabrication method of which is proposed. We estimated set and reset currents for the proposed structure by the device simulation method. Here, we confirmed that a contact area of 30 nm 2 in this structure, where Ge 2 Sb 2 Te 5 is used as PCM, provides a reset current of 13.5 µA and a set current of 4 µA, which are promising for the scaling down of PCM. Furthermore, it is confirmed that the thinner PCM in this structure provides less thermal disturbance to the neighboring cell. From the results, we expect this structure to be a promising candidate for a high-density nonvolatile memory architecture with PCM.
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